View TMUX03155_6393243.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer features multiplexes three sts-1 signals into a sonet sts-3 signal. multiplexes three au-3 signals into an sdh stm-1 (au-4) signal via a tug-3 construction. demultiplexes three sts-1 signals from a sonet sts-3 signal. demultiplexes three au-3 signals from an sdh stm-1 (au-4) signal via a tug-3 deconstruction. high-speed microprocessor interface configurable to operate with most commercial microprocessors. detects sts-3/stm-1 (au-4) loss-of-signal (los) conditions. detects sts-3/stm-1 (au-4) out-of-frame and loss-of-frame (oof/lof) conditions. provides an 8-bit bus interface at the sts-1/au-3 rate. provides a bit serial, nibble-wide, or byte-wide interface at sts-3/stm-1 (au-4) rate. provides sts-3/stm-1 (au-4) selectable scram- bler/descrambler functions and b1/b2/b3 genera- tion/detection. accepts bit rate, nibble rate, or byte rate high- speed clocks (155.52 mhz, 38.88 mhz, or 19.44 mhz, respectively). sts-3/stm-1 (au-4) internal clock and data recovery. meets type b jitter tolerance of itu-t g.958. accommodates 0.5 ui jitter up to 20 mhz. 155.52 mhz input reference clock for on-chip pll. has on-chip pll for clock synthesis, requiring only one external resistor. no output clock drift in absence of data transitions once lock is acquired. sts-1 termination mode. ?40 c to +85 c temperature range. 208-pin, shrink quad flat pack (sqfp) package. complies with gr-253-core (12/95), g.707 (3/96), g.783(1/94). applications sonet/sdh line termination equipment. sdh path origination and termination equipment. sonet/sdh add/drop multiplexers. sonet/sdh cross connects. sonet/sdh test equipment. description the TMUX03155 sts-3/stm-1 (au-4) multiplexer device provides three modes of operation: sts-3, stm-1 (au-4), and sts-1 modes. in sts-3 mode, the TMUX03155 device provides all of the functions necessary to multiplex and demultiplex up to three sts-1 signals to/from a sonet sts-3 signal. in au-4 mode, the TMUX03155 provides the functional- ity to multiplex and demultiplex up to three au-3 sig- nals to/from an stm-1 (au-4) signal. in sts-1 mode, the high-speed side of the TMUX03155 operates at 51.84 mhz and can be used for sts-1 termination and for accessing transport overhead in the sonet frame. on the sts-3/stm-1 (au-4) side, the device can be configured for either a 1-bit serial data inter- face, a 4-bit parallel (nibble-wide) data interface, or an 8-bit parallel (byte-wide) data interface. this allows the device to drive an oc3 optical signal directly or to allow for modular growth in terminal or add/drop applications. on the sts-1/au-3 side, the TMUX03155 device provides a bus mode that can communicate with up to three sts-1/au-3 devices at 19.44 mbits/s. the TMUX03155 is designed to inter- face with the agere systems inc. tmpr28051 device, or equivalent, providing complete mapping/ unmapping from/to an sts-3/stm-1 (au-4) signal for up to 84 ds1 or 63 e1 signals.
table of contents contents page 2 agere systems inc. preliminary data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer features ...................................................................................................................... ............................................. 1 applications .................................................................................................................. ............................................ 1 description ................................................................................................................... ............................................. 1 nomenclature assumptions ...................................................................................................... ................................ 7 block diagram ................................................................................................................. .........................................7 pin information ............................................................................................................... .......................................... 9 summary of i/o pins ........................................................................................................... ..............................15 mode control signals (see register description on page 54.) ................................................................... ...........16 sts-1 mode .................................................................................................................... .......................................16 transmit direction overview ................................................................................................... ...............................17 sts-1/au-3 bus mode input retiming ............................................................................................ ..................17 input select control .......................................................................................................... .................................17 sts-1/au-3 inputs ............................................................................................................. ...............................17 out-of-frame (oof) and loss-of-frame (lof) monitoring ......................................................................... .....18 descramble enable/disable ..................................................................................................... .........................18 monitor b1 and b2 errors ...................................................................................................... ............................19 h4 multiframe and pointer monitor (au-4 mode only) ............................................................................ ..........19 sts-3 generate ................................................................................................................ ................................20 transport overhead access channel (toac) insert ............................................................................... .........23 sts-3/stm-1 (au-4) scramble enable ............................................................................................ ................23 sts-3/stm-1 (au-4) b1, b2, and b3 bip generation .............................................................................. ........23 sts-3/stm-1 (au-4) loopback control ........................................................................................... .................23 sts-3/stm-1 (au-4) output interface ........................................................................................... ...................23 receive direction overview .................................................................................................... ...............................23 input retime .................................................................................................................. ....................................24 clock and data recovery ....................................................................................................... ...........................24 sts-3/stm-1 (au-4) framing .................................................................................................... .......................24 loss of signal ................................................................................................................ ....................................24 loopback select logic ......................................................................................................... .............................25 rsts-3/stm-1 (au-4) frame synchronous descrambling (sonet/sdh) .....................................................25 toac drop ..................................................................................................................... ...................................25 b1, b2, and b3 checking ....................................................................................................... ...........................25 monitoring functions .......................................................................................................... ...............................25 pointer interpretation ........................................................................................................ .................................25 data demultiplex and conversion (au-4 mode only) .............................................................................. .........26 sts-1/au-3 output byte control ................................................................................................ ......................26 b1 and b2 generate ............................................................................................................ ..............................26 sts-1/au-3 output scramble .................................................................................................... .......................27 output selection logic ........................................................................................................ ..............................27 output data formatter ......................................................................................................... .............................27 maintenance functions ......................................................................................................... .................................27 maintenance functions disabled during failure conditions ...................................................................... .......28 common maintenance and control functions ...................................................................................... ............28 transmit functions ............................................................................................................ ................................30 receive functions ............................................................................................................. ................................38 typical uses .................................................................................................................. .........................................45 section and line termination multiplex ........................................................................................ ....................45 add/drop multiplex ............................................................................................................ ................................46 digital cross connect ......................................................................................................... ...............................46 microprocessor interface ...................................................................................................... ..................................47 overview ...................................................................................................................... .....................................47
table of contents (continued) contents page agere systems inc. 3 preliminary data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor configuration modes ............................................................................................ ....................47 microprocessor interface pinout descriptions .................................................................................. .................47 microprocessor interface register architecture ................................................................................ ................49 register description .......................................................................................................... ................................54 i/o timing .................................................................................................................... ....................................101 absolute maximum ratings ...................................................................................................... ............................106 handling precautions .......................................................................................................... .................................106 operating conditions .......................................................................................................... ..................................107 electrical characteristics .................................................................................................... ..................................108 timing characteristics ........................................................................................................ ..................................110 operational timing ............................................................................................................ ..............................110 outline diagram ............................................................................................................... .....................................117 208-pin sqfp .................................................................................................................. ...............................117 ordering information .......................................................................................................... ...................................118 ds01-194pdh replaces ds00-213tic to incorporate the following updates ...................................................118
list of figures contents page 4 agere systems inc. preliminary data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer figure 1. TMUX03155 block diagram ............................................................................................. ...................... 8 figure 2. pinout of 208 sqfp device ........................................................................................... ........................ 9 figure 3. sfebe location ...................................................................................................... ............................. 33 figure 4. line termination multiplex .......................................................................................... ......................... 45 figure 5. add/drop multiplex .................................................................................................. ............................. 46 figure 6. digital cross connect ............................................................................................... ............................ 46 figure 7. mode 1?read cycle timing (mpmode = 0, mpmux = 0) ............................................................ 102 figure 8. mode 1?write cycle timing (mpmode = 0, mpmux = 0) ............................................................. 102 figure 9. mode 2?read cycle timing (mpmode = 0, mpmux = 1) ............................................................ 103 figure 10. mode 2?write cycle timing (mpmode = 0, mpmux = 1) ........................................................... 103 figure 11. mode 3?read cycle timing (mpmode = 1, mpmux = 0) .......................................................... 104 figure 12. mode 3?write cycle timing (mpmode = 1, mpmux = 0) ........................................................... 104 figure 13. mode 4?read cycle timing (mpmode = 1, mpmux = 1) .......................................................... 105 figure 14. mode 4?write cycle timing (mpmode = 1, mpmux = 1) ........................................................... 105 figure 15. single-ended input specification ................................................................................... .................. 108 figure 16. thsj0j1v1i signal structure definition ............................................................................. .............. 112 figure 17. interface data timing .............................................................................................. ......................... 115 figure 18. bus interface signals .............................................................................................. ......................... 116
list of tables contents page agere systems inc. 5 preliminary data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer table 1. pin descriptions for the 208-pin sqfp package ........................................................................ .......... 10 table 2. input/output summary ................................................................................................. ......................... 15 table 3. transmit mode control signals ........................................................................................ ..................... 16 table 4. receive mode control ................................................................................................. .......................... 16 table 5. input select control ................................................................................................. .............................. 17 table 6. expected sts-1/au-3 input frame format ............................................................................... ........... 18 table 7. sts-3 output overhead format ......................................................................................... .................. 20 table 8. stm-1 (au-4) output overhead format .................................................................................. ............. 21 table 9. sts-1/au-3 format and overhead control summary ....................................................................... ... 26 table 10. sts-1/au-3 output select control .................................................................................... .................. 27 table 11. monitors disabled during failure conditions ......................................................................... ............. 28 table 12. sfebe values ........................................................................................................ ............................. 33 table 13. g1 byte?au-4 mode only .............................................................................................. ................... 34 table 14. pfebe values ........................................................................................................ ............................. 34 table 15. value offset load values ............................................................................................ ........................ 36 table 16. transport overhead byte access?transmit direction ................................................................... .... 36 table 17. ttoac control bits .................................................................................................. ........................... 37 table 18. sts-1/au-3 overhead control ......................................................................................... ................... 42 table 19. transport overhead byte access?receive direction .................................................................... .... 44 table 20. microprocessor configuration modes .................................................................................. ................ 47 table 21. mode [1?4] microprocessor pin definitions ........................................................................... ........... 47 table 22. device-level register map ........................................................................................... ...................... 49 table 23. page 0?j1 byte insert and monitor ................................................................................... ................. 51 table 24. page 1?error counters ............................................................................................... ....................... 52 table 25. page 2?ber algorithm parameters ..................................................................................... ............. 53 table 26. register 0 (ro) ..................................................................................................... .............................. 54 table 27. registers 1?3 (ro) .................................................................................................. .......................... 54 table 28. registers 4, 5: one-shot register 0 1 (r/w) .................................................................................. 54 table 29. register 6: scratch register (r/w) .................................................................................. ................... 55 table 30. registers 7?15: delta/event (cor-ro) ................................................................................ ............ 55 table 31. registers 16?24: mask bits (r/w) .................................................................................... ................. 60 table 32. registers 25?51: state bits (ro) .................................................................................... ................... 62 table 33. register 52: mode control (r/w) ..................................................................................... ................... 64 table 34. register 53: low-speed transmit common signals (r/w) ................................................................ 65 table 35. register 54?59: transmit low-speed port input control (r/w) ........................................................ 6 6 table 36. registers 60, 61: transmit high-speed clock/port control (r/w) ...................................................... 67 table 37. register 62: transmit high-speed control signals (r/w) .............................................................. .... 68 table 38. register 62, and page 0, registers 128?191: transmit high-speed j1 insert (r/w) ....................... 69 table 39. register 62, 69: transmit high-speed control signals (r/w) .......................................................... .. 69 table 40. register 62, 66: transmit high-speed control signals (r/w) .......................................................... .. 69 table 41. registers 63?65: trace/growth bytes (r/w) ........................................................................... .......... 69 table 42. register 66: transmit f1 data byte (r/w) ............................................................................ .............. 70 table 43. registers 67 and 68: k1 and k2 insert bytes (r/w) ................................................................... ........ 70 table 44. register 69: transmit sync status byte (r/w) ........................................................................ ........... 70 table 45. register 70: path signal trace byte (r/w) ........................................................................... .............. 70 table 46. register 71: path user channel byte (r/w) ........................................................................... ............ 70 table 47. register 72: path growth byte (r/w) ................................................................................. ................. 70 table 48. register 73: tandem connection byte (r/w) ........................................................................... .......... 71 table 49. register 74: transmit high-speed line rdi insertion inhibit bits (r/w) ............................................ 71 table 50. register 75: transmit high-speed path rdi insertion inhibit bits (r/w) ............................................ 71 table 51. register 76: transmit high-speed error insert control parameters (r/w) ......................................... 72
list of tables (continued) contents page 6 agere systems inc. preliminary data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer table 52. register 77: transmit high-speed error insert control parameters (r/w) ......................................... 73 table 53. register 78: transmit high-speed error insert (r/w) ................................................................. ........ 73 table 54. register 79: receive/transmit toac control (r/w) .................................................................... ...... 74 table 55. registers 80, 81: transmit toac control (r/w) ....................................................................... ......... 75 table 56. register 83, 84: transmit high-speed sts-3/stm-1 output frame offset (r/w) ............................. 77 table 57. a1-1 alignment parameters ........................................................................................... ..................... 80 table 58. bitcnt alignment table .............................................................................................. ....................... 80 table 59. register 85: receive high/low-speed port control (r/w) .............................................................. ... 81 table 60. register 86: receive j1 and receive low-speed port select control (r/w) ..................................... 82 table 61. register 87: sts-1/au-3 receive control bits (r/w) .................................................................. ....... 82 table 62. register 88: sts-1/au-3 receive low-speed ais inhibit control bits (r/w) .................................... 83 table 63. registers 88, 89: sts-1/au-3 loss of signal detector (r/w) .......................................................... .. 83 table 64. register 90?95: continuous n times detect (cntd) values (r/w) ................................................. 83 table 65. register 95: continuous n times detect (cntd) b1 control bit (r/w) ............................................. 85 table 66. register 96: test pattern drop control and status ................................................................... .......... 86 table 67. register 97: test pattern drop error counter (ro) ................................................................... ......... 86 table 68. register 98: receive low-speed overhead control bits (r/w) ......................................................... 8 6 table 69. register 99: receive low-speed bip error insert (r/w) ............................................................... ..... 87 table 70. registers 100?102: receive low-speed overhead control bits (r/w) ............................................ 87 table 71. register 103: receive low-speed l-rdi inhibit control (r/w) ......................................................... .88 table 72. registers 104?106: receive low-speed c1 byte (r/w) .................................................................. 88 table 73. registers 107?109: receive low-speed f1 byte (r/w) .................................................................. .88 table 74. registers 110?115: receive low-speed k1, k2 byte insert (r/w) .................................................. 88 table 75. registers 116?118: receive low-speed pass control (r/w) ........................................................... 89 table 76. register 127: page control register (r/w) ........................................................................... ............. 90 table 77. page 0 - registers 128?191: j1 insert parameters (r/w) .............................................................. .. 90 table 78. page 0 - registers 192?255: j1 monitor bytes (ro) ................................................................... ...... 90 table 79. page 1 - registers 128?133: sts-1/au-3 b1 bip error counters (ro) ........................................... 90 table 80. page 1 - registers 134?140: sts-1/au-3 b2 bip error counters (ro) ........................................... 91 table 81. page 1 - registers 141?142: sts-3/stm-1 (au-4) b1 error count (ro) ......................................... 91 table 82. page 1 - registers 143?145: sts-3/stm-1 (au-4) b2 error count (ro) ......................................... 91 table 83. page 1 - registers 146?151: sts-3/stm-1 (au-4) b3 error count (ro) ......................................... 92 table 84. page 1 - registers 152?163: sts-3/stm-1 (au-4) pointer increment/decrement counter (ro) .... 92 table 85. page 1 - registers 164?166: receive high-speed sfebe count (ro) ........................................... 92 table 86. page 1 - registers 167?172: receive high-speed path febe count (ro) ..................................... 93 table 87. page 2 - register 131 (r/w) ......................................................................................... ...................... 93 table 88. page 2 - registers 128?141 (r/w) .................................................................................... ................ 94 table 89. page 2 - register 145 (r/w) ......................................................................................... ...................... 97 table 90. page 2 - registers 142?155 (r/w) .................................................................................... ................ 97 table 91. microprocessor interface i/o timing specifications .................................................................. ........ 101 table 92. recommended operating conditions .................................................................................... ........... 107 table 93. power measurements (vdd = 3.3 v, 23 c) ............................................................................. ....... 107 table 94. logic interface characteristics ..................................................................................... ..................... 108 table 95. lvds interface characteristics ...................................................................................... ................... 109 table 96. input clock specifications .......................................................................................... ....................... 110 table 97. input timing specifications ......................................................................................... ....................... 111 table 98. output clock specifications ......................................................................................... ...................... 113 table 99. output timing specifications ........................................................................................ ..................... 114
agere systems inc. 7 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer description (continued) automatic receive monitoring functions can be config- ured to provide an interrupt to the control system, or the device can be operated in a polled mode. built-in loopback at both the sts-1/au-3 and sts-3/ stm-1 (au-4) interfaces provides maximum flexibility for use in a number of sonet/sdh products including path termination multiplexers, add/drop multiplexers, and digital cross connects. a high-speed microprocessor interface and full user programmability on sts-1/au-3 to sts-3/stm-1 (au- 4) slot insertion and drop provide maximum flexibility for i/o configuration. nomenclature assumptions throughout this document, certain assumptions are made about nomenclature. the transmission path that outputs the sts-3/stm-1 (au-4) signal is called the transmit direction, while the transmission path that receives the sts-3/stm-1 (au-4) signal is referred to as the receive path. the low-speed (ls) side of the device transmits or receives the sts-1/au-3 signals, while the high-speed (hs) side of the device transmits or receives the sts-3/stm-1 (au-4) signal. the lsb (least significant bit) of a byte is labeled 0 and the msb (most significant bit) is labeled n ? 1, where n is the total number of bits in the word. a signal that ends in [3?1][7:0] implies there are three separate sig- nals, each containing 8 bits. a control bit that has only one function causes that function to be active when the control bit is set to a logic 1. for example, setting rlsclkinv, 0x57 to a logic 1 causes the low-speed output clock to be inverted. a control bit with two names performs the first choice when set to a logic 0 and the second choice when set to a logic 1. for example, tsonet_sdh, 0x34 when set to a logic 0 puts the transmit direction in the sonet mode and when set to a logic 1 puts the transmit direction in sdh mode. where necessary to avoid confusion, numbers may be expressed using a format to specify their base. the fol- lowing are examples: 9\d = 9 decimal. 0x04 = 04 hexadecimal. 11\b = 11 binary. block diagram in the transmit direction, the device outputs a clock and sync and accepts bused data [7:0] and a parity signal from up to three devices. the device outputs one data bundle at the sts-3/stm-1 (au-4) rate (clock, sync, data [7:0], and parity bit). a local clock and optional frame sync signal are needed for operation of the device. a transport overhead access channel (toac) is provided to allow overwriting of the transport over- head bytes in the output sts-3/stm-1 (au-4) frame. in the receive direction, the device accepts one sts-3/ stm-1 (au-4) bundle (clock, data, parity). optional clock and data recovery is available on the sts-3/ stm-1 (au-4) receive input. the device also accepts a loss-of-signal indication from an external source. the device outputs three sts-1/au-3 signals over a bus interface (clock, data, j0 time, parity). the sts-3/stm- 1 (au-4) input clock is used to clock this direction. a transport overhead access channel is provided for additional external monitoring of the incoming transport overhead of the sts-3/stm-1 (au-4) frame. a pointer interpreter is provided to monitor path functions. the device also has loopback capabilities at the sts- 1/au-3 and sts-3/stm-1 (au-4) interfaces. in addi- tion, the device supports sts-1 termination. an 8-bit microprocessor interface, jtag control logic, and in- circuit test capabilities are also provided.
8 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer block diagram (continued) 5-5294(f).ar.8 figure 1. TMUX03155 block diagram toac drop 3:1 mux logic spe generate 1:3 demux logic loopback select logic transport overhead loss of clock ber monitor #1r #2r #3r #1t, #2t, #3t #1r, #2r, #3r select/ logic multi- cast overhead monitor toac insert microprocessor local clock generation transmit direction receive direction s#1t s#2t s#3t tlsclko #1t #2t #3t overhead monitor interface overhead monitor bus control drop select/ logic loopback select logic add tlsspeo, tlspari tlsdata[7:0]i rlsclko bus control rlsj0timeo rlsparo rlsdata[7:0]o ttoacclko (5.184 mh z ), pointer interpreter and path monitors los framer rhslosexti ttoacsynco (8 kh z ), ttoacdatai (5.184 mbits/s) tlsv1timeo (19.44 mhz) (19.44 mhz) rtoacclko (5.184 mh z ), rtoacsynco (8 kh z ), rtoacdatao (5.184 mbits/s) thssclkot/c (155.52 mh z ), thsssyncot/c (8 kh z ), thssdataot/c (155.52 mbits/s) or rhssclkit/c (155.52 mh z ) rhssdatait/c (155.52 mbits/s) or multi- cast tlsc1j1v1timeo, thsclko (38.88 mhz or 19.44 mhz), thssynco (8 kh z ), thsdata[7:0]o (38.88 mbits/s or 19.44 mbits/s), rhsclki (38.88 mhz or 19.44 mhz), rhsdata[7:0]i (38.88 mbits/s or 19.44 mbits/s), thsparo (38.88 mbits/s or 19.44 mbits/s) rhspari (38.88 mbits/s or 19.44 mbits/s) cdr
agere systems inc. 9 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer pin information 5-4873(f) figure 2. pinout of 208 sqfp device the pin descriptions for the 208 sqfp package follow in table 1 on page 10. nc vss mode0 mode1 vdd ref5vtol thsj0j1v1i vss thsclki vdd lvds_refsel ctap_thssclki vdd thssclkit thssclkic ctap_thssj0j1v1i thssj0j1v1it thssj0j1v1ic vdd thssclkot thssclkoc vss thsssyncot thsssyncoc thssdataot thssdataoc vdd lvds_ref10 lvds_ref14 lvds_reshi lvds_reslo vss rhssclkit rhssclkic ctap_rhssclki vdd vss rhssdatait rhssdataic ctap_rhssdatai vdd vss cdr_tstmuxo rcdr10k2gnd nc rstn_tst thsclko thssynco nc nc reset vss vss vss ad5 ad6 ad7 nc cs int wr_ds rd_rw ale_as vdd rdy_dtack mpmux mpmode mpmode3ale vdd nc nc tclk vss tdi tms trst tdo vdd scan_en test_mode nc ict vss ref5vtol nc nc nc vdd ttoacclko ttoacsynco ttoacdatai vdd rtoacclko rtoacsynco rtoacdatao vdd nc nc nc nc rhslosexti rhsclki vss nc 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 vss vss rhspari rhsdata7i rhsdata6i rhsdata5i rhsdata4i rhsdata3i rhsdata2i rhsdata1i rhsdata0i nc vdd nc nc nc nc nc nc nc vdd vss nc nc nc nc vss vdd nc nc nc vss vdd nc nc nc nc nc nc nc vdd thsdata0o thsdata1o thsdata2o thsdata3o thsdata4o thsdata5o thsdata6o thsdata7o thsparo vss nc 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 nc vss ad4 ad3 ad2 ad1 ad0 a7 a6 a5 a4 a3 vdd a2 a1 a0 rlsparo reserved rlsdata0o rlsdata1o rlsdata2o vss rlsdata3o rlsdata4o rlsdata5o rlsdata6o vss rlsdata7o vdd rlsclko nc vss rlsj0timeo nc tlsspeo tlsv1time0 tlsclko tlsj0j1v1timeo tlsdata7i tlsdata6i vdd tlsdata5i tlsdata4i tlsdata3i tlsdata2i tlsdata1i tlsdata0i tlspari nc nc vss vss 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
10 10 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer pin information (continued) table 1. pin descriptions for the 208-pin sqfp package * pin order follows symbol order, e.g., pin 170 refers to tlsdata7i. ? i = input, o = output, i/o = bidirectional signal, i d = input with internal pull-down (~20 kw), i u = input with internal pull-up (~100 kw), i diff or o diff = differential input or output. all i/o not explicitly stated with a buffer type are 5 v compatible. they will tolerate 5 v at their inputs or out- puts. lvds = low-voltage differential signal. pin * symbol type ? name/description transmit direction signals 143, 142 thssclkit/c i diff lvds transmit high-speed serial clock input. the transmit clock can either be 155.52 mhz (serial), 38.88 mhz (nibble), or 19.44 mhz (byte). 145 ctap_thssclki i center tap for transmit high-speed serial clock input. the cen- ter tap input provides for center-tapped common-mode termination. this input should be terminated through an external capacitor to ground (approximately 0.1 f). 140, 139 thssj0j1v1it/c i diff lvds transmit high-speed serial sync input. the transmit sync signal is active during j0 time (8 khz), j11 time, and v11 time (2 khz). this signal is active-high and is optional. (see figure 16 on page 112 for details.) 141 ctap_thssj0j1v1i i center tap for transmit high-speed serial sync input. the cen- ter tap input provides for center-tapped common-mode termination. this input should be terminated through an external capacitor to ground (approximately 0.1 f). 148 thsclki i d transmit high-speed clock input . the transmit clock can either be 38.88 mhz (nibble) or 19.44 mhz (byte). 150 thsj0j1v1i i d transmit high-speed sync input. the transmit sync signal is active during j0 time (8 khz), j11 time, and v11 time (2 khz). this signal is active-high and is optional. 172 tlsclko o transmit low-speed output clock. the sts-1/au-3 clock will be 19.44 mhz. 174 tlsspeo o transmit low-speed synchronous payload envelope (spe) . the sts-1/au-3 spe signal is low when the transport overhead is on the input bus (tlsdata[7:0]i). (see figure 18 on page 116 for details.) 171 tlsj0j1v1timeo o transmit low-speed j0, j1, and v1 time signal. j0 time is defined when tlsspeo is a logic 0, tlsj0j1v1timeo is a logic 1, tlsv1timeo is a logic 0, and the j0 byte is on the input bus. j1 time is defined when tlsspeo is a logic 1, tlsj0j1v1timeo is a logic 1, tlsv1timeo is a logic 0, and j11 is on the input bus. (see figure 18 on page 116 for details.) 173 tlsv1timeo o transmit low-speed v1 time. this signal is active-high when the current frame contains the v1 byte. v1 time is defined when tlsspeo is a logic 1, tlsj0j1v1timeo is a logic 1, and tlsv1timeo is a logic 1. (see figure 18 on page 116 for details.) 170, 169, 167?162 tlsdata[7:0]i i d transmit low-speed data. tlsdata7i is the most significant bit of the input byte. (see figure 18 on page 116 for details.)
agere systems inc. 11 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer pin information (continued) table 1. pin descriptions for the 208-pin sqfp package (continued) * pin order follows symbol order, e.g., pin 170 refers to tlsdata7i. ? i = input, o = output, i/o = bidirectional signal, i d = input with internal pull-down (~20 kw), i u = input with internal pull-up (~100 kw), i diff or o diff = differential input or output. all i/o not explicitly stated with a buffer type are 5 v compatible. they will tolerate 5 v at their inputs or out- puts. lvds = low-voltage differential signal. pin * symbol type ? name/description transmit direction signals (continued) 161 tlspari i u transmit low-speed parity bit. the sts-1/au-3 parity input is only defined for byte-wide data. the device can be provisioned to receive either odd or even parity. 137, 136 thssclkot/c o diff lvds transmit high-speed serial clock. the sts-3/stm-1 (au-4) clock will be 155.52 mhz for serial output data; otherwise, this output is placed in a high-impedance state. 134, 133 thsssyncot/c o diff lvds transmit high-speed serial sync . the sts-3/stm-1 (au-4) 8 khz frame sync is coincident with the first or last bit of the frame. 132,131 thssdataot/c o diff lvds transmit high-speed serial data. if the device is operating in the serial mode, then this output is used as the differential data pin. in nibble or parallel output mode, this output is placed in a high- impedance state. 110 thsclko o transmit high-speed clock. the sts-3/stm-1 (au-4) clock is 38.88 mhz for nibble data, or 19.44 mhz for byte-wide data. 109 thssynco o transmit high-speed sync . the sts-3/stm-1 (au-4) 8 khz frame sync is coincident with the first or last nibble/byte of the frame. 101?94 thsdata[7:0]o o transmit high-speed data. bit 7 is the most significant bit in nibble or byte mode. 102 thsparo o transmit high-speed parity. the parity output is only defined for nibble or byte-wide data. the device can be provisioned to source either an odd or even parity bit. sts-3/stm-1 (au-4) transport overhead access channel (toac) insert 37 ttoacclko o transmit toac clock. (5.184 mhz.) 38 ttoacsynco o transmit toac sync. (8 khz.) 39 ttoacdatai i d transmit toac data. (5.184 mbits/s.)
12 12 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer pin information (continued) table 1. pin descriptions for the 208-pin sqfp package (continued) * pin order follows symbol order, e.g., pin 170 refers to tlsdata7i. ? i = input, o = output, i/o = bidirectional signal, i d = input with internal pull-down (~20 kw), i u = input with internal pull-up (~100 kw), i diff or o diff = differential input or output. all i/o not explicitly stated with a buffer type are 5 v compatible. they will tolerate 5 v at their inputs or out- puts. lvds = low-voltage differential signal. pin * symbol type ? name/description receive direction signals 124, 123 rhssclkit/c i diff lvds receive high-speed serial clock input. the sts-3/stm-1 (au-4) serial clock is 155.52 mhz. 122 ctap_rhssclki i center tap for receive high-speed serial clock input. the cen- ter tap input provides for center-tapped common-mode termination. this input should be terminated through an external capacitor to ground (approximately 0.1 f). 119, 118 rhssdatait/c i diff lvds receive high-speed serial data input. the sts-3/stm-1 (au-4) serial data is 155.52 mbits/s. 117 ctap_rhssdatai i center tap for receive high-speed serial data input. the center tap input provides for center-tapped common-mode termination. this input should be terminated through an external capacitor to ground (approximately 0.1 f). 113 rcdr10k2gnd i receive cdr bias resistor input. must be tied to ground, through an external 10 k ? 1% resistor. 50 rhsclki i d receive high-speed clock input. the sts-3/stm-1 (au-4) clock is 38.88 mhz (nibble), or 19.44 mhz for byte-wide data. 56?63 rhsdata[7:0]i i d receive high-speed data inputs. data bit 7 is the most significant bit in nibble or byte mode. 55 rhspari i u receive high-speed input parity. the parity input is only defined for nibble- or byte-wide data. the device can be provisioned to accept either odd or even parity. 49 rhslosexti i d receive high-speed loss of signal . this is an active-high signal. 179 rlsclko o receive sts-1/au-3 output clock . the sts-1/au-3 clock will be 19.44 mhz for byte-wide data (bus mode). 176 rlsj0timeo o receive sts1/au-3 output j0 time . this signal will be active (logic 1) each time the j0 byte is output. 181, 183?186, 188?190 rlsdata[7:0]o o receive sts-1/au-3 output data . rlsdata7o is the most signifi- cant bit of the output byte. 192 rlsparo o receive sts-1/au-3 output parity. the device can be provisioned to source either an odd or even parity bit per byte transfer. sts-3/stm-1 (au-4) transport overhead access channel (toac) drop 41 rtoacclko o receive toac clock. (5.184 mhz.) 42 rtoacsynco o receive toac sync. (8 khz.) 43 rtoacdatao o receive toac data. (5.184 mbits/s.)
agere systems inc. 13 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer pin information (continued) table 1. pin descriptions for the 208-pin sqfp package (continued) * pin order follows symbol order, e.g., pin 170 refers to tlsdata7i. ? i = input, o = output, i/o = bidirectional signal, i d = input with internal pull-down (~20 kw), i u = input with internal pull-up (~100 kw), i diff or o diff = differential input or output. all i/o not explicitly stated with a buffer type are 5 v compatible. they will tolerate 5 v at their inputs or out- puts. lvds = low-voltage differential signal. pin * symbol type ? name/description mode/in-circuit test and reset control inputs 30 ict i u in-circuit test control (active-low). if ict is forced low, certain output pins are placed in the high-impedance state. 106 reset i u hardware reset (active-low). if reset is forced low, all internal states in the transceiver paths are reset and data flow through each channel will be interrupted. 111 rstn_tst i u test reset (active-low) . this pin is for test purposes only; it should be left unconnected. 153, 154 mode [1:0] i u , i d mode control . normal sts-3/stm-1 mode set mode [1:0] = 10. sts-1 mode set mode [1:0] = 00 microprocessor interface 14 mpmux i microprocessor multiplex mode. setting mpmux = 1 allows the microprocessor interface to accept the multiplexed address and data signals. setting mpmux = 0 allows the microprocessor interface to accept demultiplexed (separate) address and data signals. 15 mpmode i microprocessor mode. when mpmode = 1, the device uses the address latch enable type microprocessor read/write protocol with separate read and write controls. setting mpmode = 0 allows the device to use the address strobe type microprocessor read/write pro- tocol with a separate data strobe and a combined read/write control. 16 mpmode3ale i u microprocessor mode3 ale enable. when the device is in mode3 (mpmode = 1 and mpmux = 0), the ale signal can be used to retime the address or the address bus can be used directly without being retimed. this is an active-high signal. 9 wr _ds i write (active-low). if mpmode = 1, this pin is asserted low by the microprocessor to initiate a write cycle. data strobe (active-low). if mpmode = 0, this pin becomes the data strobe for the microprocessor. when r/ w = 0 (write), a low applied to this pin latches the signal on the data bus into internal reg- isters. 11 ale_as i address latch enable. if mpmode = 1, this pin becomes the address latch enable for the microprocessor. when this pin transi- tions from high to low, the address bus inputs are latched into the internal registers. address strobe (active-low). if mpmode = 0, this pin becomes the address strobe for the microprocessor. when this pin transitions from high to low, the address bus inputs are latched into the internal registers. 10 rd _r/w i read (active-low). if mpmode = 1, this pin is asserted low by the microprocessor to initiate a read cycle. read/write. if mpmode = 0, this pin is asserted high by the micro- processor to indicate a read cycle or asserted low to indicate a write cycle.
14 14 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer pin information (continued) table 1. pin descriptions for the 208-pin sqfp package (continued) * pin order follows symbol order, e.g., pin 170 refers to tlsdata7i. ? i = input, o = output, i/o = bidirectional signal, i d = input with internal pull-down (~20 kw), i u = input with internal pull-up (~100 kw), i diff or o diff = differential input or output. all i/o not explicitly stated with a buffer type are 5 v compatible. they will tolerate 5 v at their inputs or out- puts. lvds = low-voltage differential signal. pin * symbol type ? name/description microprocessor interface (continued) 7 cs i u chip select (active-low). this pin is asserted low by the micropro- cessor to enable the microprocessor interface. if mpmux = 1, an internal 100 k ? pull-up is on this pin. 8into interrupt. this pin is asserted high to indicate an interrupt produced by an alarm condition. the activation of this pin can be masked by the microprocessor by setting the appropriate mask bits. 13 rdy_dtack o ready. if mpmode = 1, this pin is asserted high to indicate the device has completed a read or write operation. this pin is in a high- impedance state when cs is high. data transfer acknowledge (active-low). if mpmode = 0, this pin is asserted low to indicate the device has completed a read or write operation. 5?3, 206?202 ad[7:0] i/o microprocessor interface address/data bus. if mpmux = 0, these pins become the bidirectional, 3-state data bus. if mpmux = 1, these pins become the multiplexed address/data bus. 201?197, 195?193 a[7:0] i d microprocessor interface address. if mpmux = 0, these pins become the address bus for the microprocessor interface registers. jtag signals 20 tclk i u jtag clock. 22 tdi i u jtag input data. 23 tms i u jtag mode select. 24 trst i u jtag reset (active-low). 25 tdo o jtag output data. scan specific inputs 27 scan_en i u scan enable. place device in scan mode (active-low). 28 test_mode i d test mode. disable all clocks and async resets (active-high). 114 cdr_tstmux0 o cdr test output. test purpose only. lvds control signals 146 lvds_refsel i u lvds reference select. if lvds_refsel = 0, then use external 1.0 and 1.4 reference voltages. if lvds_refsel = 1, then use inter- nal references. 129 lvds_ref10 i 1.0 v reference for lvds buffers. this signal is optional. 128 lvds_ref14 i 1.4 v reference for lvds buffers. this signal is optional. 127 lvds_reshi i lvds resistor pins. a 100 ? 1% resistor must be placed between these two pins when using the lvds buffers. 126 lvds_reslo i
agere systems inc. 15 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer pin information (continued) table 1. pin descriptions for the 208-pin sqfp package (continued) * pin order follows symbol order, e.g., pin 170 refers to tlsdata7i. ? i = input, o = output, i/o = bidirectional signal, i d = input with internal pull-down (~20 kw), i u = input with internal pull-up (~100 kw), i diff or o diff = differential input or output. all i/o not explicitly stated with a buffer type are 5 v compatible. they will tolerate 5 v at their inputs or out- puts. lvds = low-voltage differential signal. summary of i/o pins pin * symbol type ? name/description power and ground pins 1?2, 21 31, 51, 53?54, 74, 79, 84, 103, 105, 115, 120, 125, 135, 149, 155, 157?158, 177, 182, 187, 207 v ss i ground reference. 12, 17, 26, 36, 40, 44, 65, 73, 80, 85, 93, 116, 121, 130, 138, 144, 147, 152, 168, 180, 196 v dd i power supply for digital circuitry. 151, 32 ref5vtol i 5 v tolerant reference voltage. table 2. input/output summary type number of pins input differential 8 single ended 57 output differential 6 single ended 35 bidirectional 8 total signal 114 no connect (reserved) 45 ref5vtol 2 lvds_ref10 1 lvds_ref14 1 v dd 21 v ss (gnd) 24 total package 208 sqfp
16 16 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer mode control signals (see register description on page 54.) the device is controlled by four control signals: t/rsonet_sdh and t/rsts3_au4, 0x34 . these signals control the following: the type of input signal to expect (low-speed (ls) side?sts-1/au-3). the expected high-speed (hs) input/output signal format?sts-3/stm-1 (au-4), or sts-1. the default byte value in the outgoing hs frame. these provisioning signals are summarized in table 3 and table 4. sts-1 mode in sts-1 mode, all other device functions remain the same as in sts-3/stm-1 mode; except, the device runs at one-third the sts-3/stm-1 rate and operates on a single sts-1 frame. the high-speed side operates in the follow- ing three modes: 1) as a 51.84 mbits/s serial interface, 2) as a parallel 12.96 mhz nibble wide, 3) or as a 6.48 mhz byte-wide interface. the low-speed sts-1/au-3 side operates at 6.48 mbytes/s and communicates with a single sts-1/au-3 device (tmpr28051). since the toac interface provides access to the transport overhead in a single sts-1 frame, its clock and data operate at 1.782 mhz, while the sync runs at 8 khz. for sts-1 mode, set both mode pins 153 and 154 to a logic 0, and set all mode control bits tsts3_au4, tsonet_sdh, rsts3_au4, rsonet_sdh, 0x34 , to a logic 0. table 3. transmit mode control signals tsts3_au4 tsonet_sdh description 0 = sts-3 0 = sonet 1 1. sonet = oof 0 1, 4 times detect; default output byte = 0x00. three sts-1 inputs multiplexed to an sts-3 output. also used for sts-1 mode. see sts-1 mode section for details. 1 = au-4 0 = sonet * three au-3 signals multiplexed to an stm-1 (au-4) signal. 0 = sts-3 1 = sdh 2 2. sdh = oof 0 1, 5 times detect; default output byte = 0xff. three sts-1 inputs multiplexed to an sts-3 output. 1 = au-4 1 = sdh ? three au-3 signals multiplexed to an stm-1 (au-4) signal. table 4. receive mode control rsts3_au4 rsonet_sdh description 0 = sts-3 0 = sonet 1 1. sonet = oof 0 1, 4 times detect; default output byte = 0x00; ignore ss bits. one sts-3 input demultiplexed to three sts-1 outputs. also used for sts-1 mode. see sts-1 mode section for details. 1 = au-4 0 = sonet * one stm-1 (au-4) input demultiplexed to three au-3 outputs. 0 = sts-3 1 = sdh 2 2. sdh = oof 0 1, 5 times detect; default output byte = 0xff; verify ss bits = 10. one sts-3 input demultiplexed to three sts-1 outputs. 1 = au-4 1 = sdh ? one stm-1 (au-4) input demultiplexed to three au-3 outputs.
agere systems inc. 17 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer transmit direction overview the following major functions are performed in the transmit direction: sts-1/au-3 bus mode retiming, input select control, sts-1/au-3 inputs, out-of-frame (oof) and loss-of frame (lof) monitoring, descramble enable/disable, monitor b1 and b2 errors, h4 multiframe and pointer monitor (au-4 mode only), sts-3 generate, stm-1 (au-4) frame generation (au-4 mode), transport overhead access channel (toac) insert, sts-3/stm-1 (au-4) scramble enable, sts-3/stm-1 (au-4) loopback control, and sts-3/stm-1 (au-4) output interface. sts-1/au-3 bus mode input retiming the bus mode provides a single byte-wide bus and parity bit that is shared with up to three devices at 19.44 mbits/s. the device will source a clock (19.44 mhz), synchronous payload envelope (spe) indicator, j0j1v1 indicator, and v1 time indicator signals toward the downstream devices. these signals guarantee frame alignment between all three sts-1/au-3 inputs and h4 byte multiframe values (au-4 mode). the v1 time signal can be dis- abled under software control ( tlsv1disable, 0x35 ). the clock can be inverted leaving the device ( tlsclkinv, 0x35 ). an odd/even parity bit ( tlsvoepar, 0x35 ) is verified per byte transfer ( tlspare[3?1], tlsparm[3?1], 0x07, 0x10 ). input select control this function determines which signals are multiplexed to form the sts-3 signal. these control bits ( tsel[3? 1][2:0], 0x3a, 0x38, 0x36 ) allow loopback (sts-1/au-3-r to sts-1/au-3-t), input shuffle, and multicast opera- tions to be possible. the selected sts-1/au-3 inputs are labeled s#1t, s#2t, and s#3t in figure 1. sts-1/au-3 inputs the sonet/sdh sts-1/au-3 frame is comprised of 9 rows x 90 columns that repeat at an 8 khz rate. each col- umn is 1-byte wide. the frame contains three columns of transport overhead, one column of path overhead, and 86 columns of payload. for column byte definitions, see table 6 on page 18. table 5. input select control tsel [3?1][2:0] output 000 (0) sts-1/au-3 #1 transmit 001 (1) sts-1/au-3 #2 transmit 010 (2) sts-1/au-3 #3 transmit 011 (3) sts-1/au-3 #1 receive (loopback) sts3 mode only 100 (4) sts-1/au-3 #2 receive (loopback) sts3 mode only 101 (5) sts-1/au-3 #3 receive (loopback) sts3 mode only 110 (6) sts-1/au-3 #1 transmit 111 (7) sts-1/au-3 #1 transmit
18 18 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer transmit direction overview (continued) sts-1/au-3 inputs (continued) the 27 bytes of transport overhead from each sts-1/au-3 input must be aligned * (a1-1, a1-2, a1-3 must all be coincident from all three sts-1/au-3 inputs) and are allocated as shown in table 6 . ? monitored in sts-1 mode. ? monitored in au-4 mode. note: x = don?t care (payload). the path overhead (poh) can start anywhere within the spe and cannot be accessed in the sts-3 mode. in the au-4 mode, the pointer is fixed at 522\d; therefore, the j1 byte will always be in row 1, column 4. the h4 byte is the only valid byte in the poh and all other bytes are ignored. out-of-frame (oof) and loss-of-frame (lof) monitoring the device monitors for out-of-frame (oof) and loss-of-frame (lof) states on each selected sts-1/au-3 input ( tlsoof[3?1] , tlsoofd[3?1] , tlsoofm[3?1] , tlslof[3?1] , tlslofd[3?1 , tlslofm[3?1], 0x08, 0x11, 0x19 ). each input will be considered out-of-frame until two successive framing patterns (0xf628) separated in time by 125 s occur without framing byte errors. each selected sts-1/au-3 input will be considered in frame until five (sdh)/four (sonet) successive frames separated in time by 125 s occur with errored framing patterns. the device will be considered in the lof state when an oof condition persists for 24 consecutive frames (3 ms) or clear when the oof condition is inactive for 24 consecutive frames (3 ms) with the correct framing patterns spaced 125 s apart. descramble enable/disable each selected sts-1/au-3 input can be descrambled ( tlsdscr[3?1], 0x3a, 0x38, 0x36 ) according to the frame synchronous descrambling sequence 1 + x 6 + x 7 . the sequence is reset to 1111111 at the beginning of the byte following the c1 byte and descrambles all of the sts-1/au-3 data except the a1, a2, and j0 bytes. writing a logic 1 to the appropriate bit causes the selected sts-1/au-3 signal to be descrambled. * can be provided by the agere tmpr28051 mapper device. table 6. expected sts-1/au-3 input frame format transport overhead payload col. 1 col. 2 col. 3 col. 4 col. 5?90 row 1 a1 ?? a2 ?? j0 j1 x row 2 b1 ?? e1 f1 b3 x row 3d1d2d3c2 x row 4 h1 ? h2 ? h3 g1 x row 5 b2 ?? k1 k2 f2 x row 6 d4 d5 d6 h4 ? x row 7 d7 d8 d9 z3 x row 8 d10 d11 d12 z4 x row 9 s1 m0 e2 z5 x
agere systems inc. 19 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer transmit direction overview (continued) monitor b1 and b2 errors the device verifies b1 and b2 bit interleaved parity (bip) values on each selected sts-1/au-3 input. the device will count bip errors or block errors under software control ( bitblockcnt, tlsb1ecnt[3?1][15:0], tlsb2ecnt[3?2][15:0], tlsb2ecnt1[17:0], 0x34, page 1 - 0x80?0x85, page 1 - 0x86?0x88, page 1 - 0x89?0x8c ). these counters will update on latch_cnt, 0x04 and are large enough to store at least 1 second?s worth of data. h4 multiframe and pointer monitor (au-4 mode only) in this mode, all three input signals are required to have pointer values (h1, h2) with the same fixed value of 522\d. this ensures the j1 byte starts in row 1, column 4. the h4[1:0] multiframe bits must be the same from all inputs and equal to the internally expected value. this is required because the output stm-1 (au-4) signal only has one h4 byte. the device will synchronize its h4 internal expected value to a 1 after detecting an embedded 2 khz sync in the local frame sync signal (ths(s)j0j1v1i(t/c)). the device will declare a pointer match after two consecutive pointer values of 522\d are detected 125 s apart. a pointer mismatch will be declared after five successive frames separated in time by 125 s occur with errored pointer values ( tlsptrmis[3?1] , tlsptrmisd[3?1] , tlsptrmism[3?1], 0x1a, 0x09, 0x12 ). the device will declare an h4 multiframe match after two consecutive h4 values match the expected value spaced 125 s apart. an h4 multiframe mismatch will be declared after five successive frames separated in time by 125 s occur with h4 values not equal to the expected value ( tlsh4mis[3?1] , tlsh4misd[3?1] , tlsh4mism[3?1], 0x1a, 0x09, 0x12 ).
20 20 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer transmit direction overview (continued) sts-3 generate the device will create the overhead according to table 7. the poh byte locations are not fixed and cannot be accessed. * access through transmit toac (see table 17 on page 37). note: bold type within the table is not defined in the standard and is labeled here for clarity. the following values are assigned to the transmitted overhead bytes: a1?11110110 (0xf6) a2?00101000 (0x28) j0? tj0dins[7:0], 0x3f z0-2? tz02dins[7:0], 0x40 z0-3? tz03dins[7:0], 0x41 b1?variable value (bip-8 parity) f1?variable value tf1dins[7:0], 0x42 h1-1, 2, 3?passed through from respective sts-1 h2-1, 2, 3?passed through from respective sts-1 h3-1, 2, 3?passed through from respective sts-1 b2-1, 2, 3?variable value (bip-24) k1?variable value tapsins[12:5], 0x43, 0x44 k2?variable value tapsins[4:0] , tk2ins[2:0], 0x43, 0x44 ?rdi-l, ais-l s1?variable value ts1dins[7:0], 0x45 m1?variable value (section febe?number of b2 errors) tsfebeinh, 0x3e all bytes not specified above, either: (1) are set to the fixed stuff value (0x00 (sonet)). (2) are toac value-inserted. (3) have passed through from the selected sts-1 input, all under software control. the variable values are described beginning on page 30 in the maintenance functions section of this document. table 7. sts-3 output overhead format sts-3 overhead col. 1 col. 2 col. 3 col. 4 col. 5 col. 6 col. 7 col. 8 col. 9 col. 10?270 row 1 a1-1 a1-2 a1-3 a2-1 a2-2 a2-3 j0 z0-2 z0-3 payload row 2 b1 b1-2 * b1-3 *e1* e1-2 * e1-3 *f1* f1-2 * f1-3 * row 3 d1* d1-2 * d1-3 *d2* d2-2 * d2-3 *d3* d3-2 * d3-3 * row 4 h1-1 h1-2 h1-3 h2-1 h2-2 h2-3 h3-1 h3-2 h3-3 row 5 b2-1 b2-2 b2-3 k1 k1-2 * k1-3 *k2 k2-2 * k2-3 * row 6 d4* d4-2 * d4-3 *d5* d5-2 * d5-3 *d6* d6-2 * d6-3 * row 7 d7* d7-2 * d7-3 *d8* d8-2 * d8-3 *d9* d9-2 * d9-3 * row 8 d10* d10-2 * d10-3 *d11* d11-2 * d11-3 *d12* d12-2 * d12-3 * row 9 s1* z1-2* z1-3* z2-1* z2-2 *m1 e2* e2-2 * e2-3 *
agere systems inc. 21 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer transmit direction overview (continued) stm-1 (au-4) frame generation (au-4 mode) the device will create the overhead according to the following table. the path overhead bytes are created in this mode. the three au-3 inputs are converted to tug-3 format and inserted into a vc-4 that is multiplexed into an au-4. * access through transmit toac (see table 17 on page 37). note: bold type within the table is not defined in the standard and is labeled here for clarity. the following values are assigned to the transmitted overhead bytes: a1?11110110 (0xf6) a2?00101000 (0x28) j0?variable value tj0dins[7:0], 0x3f z0-2?variable value tz02dins[7:0], 0x40 z0-3?variable value tz03dins[7:0], 0x41 b1?variable value (bip-8 parity) f1?variable value tf1dins[7:0], 0x42 h1-1?01101010 h2-1?00001010 (pointer value of 522\d) y?10011011 (ndf, ss, ptr)?concatenation indication 1 ? ?all ones pattern h3-1, 2, 3?default byte value (0xff) b2-1, 2, 3?variable value bip-24 k1?variable value tapsins[12:5], 0x43, 0x44 k2?variable value tapsins[4:0], tk2ins[2:0], 0x43, 0x44 ?rdi-l, ais-l s1?variable value ts1dins[7:0], 0x45 m1?variable value (section febe?number of b2 errors) tsfebeinh, 0x3e ? access through transmit toac. table 8. stm-1 (au-4) output overhead format stm-1 (au-4) overhead au-4 payload col. 1 col. 2 col. 3 col. 4 col. 5 col. 6 col. 7 col. 8 col. 9 poh 10 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 22? 270 row 1 a1-1 a1-2 a1-3 a2-1 a2-2 a2-3 j0 z0-2 z0-3 j1 f i x e d s t u f f f i x e d s t u f f n p i n p i n p i f i x e d s t u f f f i x e d s t u f f f i x e d s t u f f t u g - 3 a t u g - 3 b t u g - 3 c ? row 2 b1 b1-2 * b1-3 *e1* e1-2 * e1-3 *f1* f1-2 * f1-3 *b3 ? row 3 d1* d1-2 * d1-3 *d2* d2-2 * d2-3 *d3* d3-2 * d3-3 *c2 ? row 4 h1-1 y y h2-1 1* 1* h3-1 h3-2 h3-3 g1 s t u f f s t u f f s t u f f ? row 5 b2-1 b2-2 b2-3 k1 k1-2 * k1-3 *k2 k2-2 * k2-3 *f2 ? row 6 d4* d4-2 * d4-3 *d5* d5-2 * d5-3 *d6* d6-2 * d6-3 *h4 ? row 7 d7* d7-2 * d7-3 *d8* d8-2 * d8-3 *d9* d9-2 * d9-3 *z3 ? row 8 d10* d10-2 * d10-3 *d11* d11-2 * d11-3 *d12* d12-2 * d12-3 *z4 ? row 9 s1* z1-2* z1-3* z2-1* z2-2* m1 e2* e2-2 * e2-3 *z5 ?
22 22 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer transmit direction overview (continued) stm-1 (au-4) frame generation (au-4 mode) (continued) path bytes j1?64-byte programmable sequence tj1ins, 0x3e, tj1dins[64?1][7:0], 0x3e, 0x80?0xbf b3?variable value bip-8 c2? tc2dins[7:0], 0x46 g1[7:4]?reicnt (b3 errors from receive side) tpfebeeins, 0x4d g1[3]?rdi indication tprdiins, 0x4b g1[2:0]?default value f2?variable value tf2dins[7:0], 0x47 h4[1:0]?position indicator (multiframe value (00\b to 11\b)) z3?variable value tz3dins[7:0], 0x48 z4?default value z5?variable value tz5dins[7:0], 0x49 fixed stuff = depends on tsonet_sdh, 0x34 value (sonet = 0x00, sdh = 0xff) npi (null pointer indicator?byte 1, byte 2, and byte 3) = (10011011, 11100000, 11111111). npi is generated for compatibility with older devices. all bytes not specified above, either: (1) are set to the fixed stuff value 0xff (sdh). (2) are toac value inserted. (3) have passed through from the selected au-3 input, all under user control.
agere systems inc. 23 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer transmit direction overview (continued) transport overhead access channel (toac) insert the device will allow the insertion of overhead data from the transmit toac under user control. (see ttoac in the maintenance functions section, page 36, for more details.) sts-3/stm-1 (au-4) scramble enable scrambling of the sts-3/ stm-1 (au-4) signal is provisionable ( thsscr, 0x3d ). a frame synchronous scram- bling sequence 1 + x 6 + x 7 is used. the sequence is reset to 1111111 at the beginning of the byte following the z0- 3 byte and scrambles all of the sts-3/stm-1 (au-4) data except all the a1, a2 and j0, z0 bytes. writing a logic 1 to this bit causes the signal to be scrambled. sts-3/stm-1 (au-4) b1, b2, and b3 bip generation the device will generate a b1-bip-8, b2-bip-24, and a b3-bip-8 (au-4 mode only) on the output signal. each bip calculator can be programmed to insert an inverted bip value ( thsb1errins , thsb2errins[3?1] , thsb3errins, 0x4c ). sts-3/stm-1 (au-4) loopback control the output sts-3/stm-1 (au-4) signal can be replaced by the receive sts-3/stm-1 (au-4) signal under software control ( rhs2thslb, 0x3d ). the output format (bit, nibble, or byte) will be the same as the receive input format not the transmit output port format. note: the transmit port type must be programmed to be the same as the receive input type. sts-3/stm-1 (au-4) output interface the transmit sts-3/stm-1 (au-4) output can either be serial at 155.52 mbits/s, nibble at 38.88 mbits/s, or byte at 19.44 mbits/s. this is controlled by writing to thsptype[1:0], 0x3c . the data is clocked out of the device on the rising edge of the clock. this clock can be inverted leaving the device ( thsclkinv, 0x3c ). when provisioned in the parallel or nibble mode, an even or odd parity bit is generated per transfer ( thsparoeg, 0x3c ). the output sync can be programmed to be active on the first clock cycle of the frame (a1-1 coincident with sync) or the last clock cycle of the frame ( thssa1orend, 0x3c ). the output clock, sync, and data signals can be placed in a high-impedance state under user control ( thschiz = 1, thsshiz = 1, thsdhiz = 1, 0x3d ). unused outputs in serial and nibble mode will be placed in a high- impedance state automatically by the device. receive direction overview the following functions are performed in the receive direction: input retime, clock and data recovery, sts-3/stm-1 (au-4) framing, loss-of-signal detection, loopback select logic, rsts-3/stm-1 (au-4) frame synchronous descrambling, toac drop, b1, b2, and b3 checking, monitoring functions, pointer interpretation, data demultiplex and conversion (au-4 mode only), sts-1/au-3 output byte control, b1 and b2 generate, sts-1/au-3 output scramble, output selection logic, and output data formatter.
24 24 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer receive direction overview (continued) input retime the device accepts either a serial 155.52 mhz-mbits/s, nibble 38.88 mhz-mbits/s, or byte parallel 19.44 mhz- mbits/s clock-data sts-3/stm-1 (au-4) input. this is controlled by writing to rhsptype[1:0], 0x55 . the user can configure which edge of the clock to use to retime the data. rhsedge, 0x55 = 1 uses the rising edge; rhsedge = 0 uses the falling edge. if in nibble or parallel mode, an odd/even parity bit ( rhsvoepar, 0x55 ) is verified per transfer ( rhspare , rhsparm, 0x0a, 0x13 ), otherwise, this indicator is disabled. clock and data recovery the device provides an optional clock and data recovery circuit (cdr) on the serial sts-3/stm-1(au-4) input. the cdr aligns the sts-3/stm-1 data signal to a local clock and then outputs a retimed data and clock signal. the input data and local clock rates need not be synchronous. the cdr only works at the nominal 155 mbits/s rate and uses the high-speed transmit input clock (thssclkit/c) as a reference for the local clock. the cdr is enabled by the rhsporcdrsel bit, 0x57 . sts-3/stm-1 (au-4) framing the device will frame on the input sts-3/stm-1 (au-4) signal. the state of the framer ( rhsoof ), as well as any changes to this state ( rhsoofd , rhsoofm, 0x0a, 0x13 ), will be reported. a loss-of-frame ( rhslof, 0x1b ) state bit, as well as any changes to this state ( rhslofd , rhslofm, 0x0a, 0x13 ), will be reported. framing algorithm the 32-bit (a1-2, a1-3, a2-1, a2-2) framing pattern will be used in the frame detection. the device will be consid- ered out of frame until two successive framing patterns separated in time by 125 s occur without framing byte errors. the device will be considered in frame until five (sdh)/four (sonet) successive frames separated in time by 125 s occur with errored framing patterns. if the framer transitions to the out-of-frame state, the framer will remain synchronized to the last known frame boundary or the latest detected unerrored framing pattern. the device will be considered in the loss-of-frame state (lof) when an oof condition persists for 24 consecutive frames (3 ms). the device will transition out of the lof state after receiving 24 consecutive frames with the correct framing patterns spaced 125 s apart and the oof condition is clear. loss of signal the device will detect a loss-of-signal condition by monitoring a unique input signal pin (rhslosexti) or detect- ing a continuous all-zeros/all-ones pattern for 51.44 ns to 105 s in 51.44 ns steps ( losdetcnt[10:0], 0x58? 0x59 ) before data is descrambled. to recover from the los state receiving two consecutive frames with the correct framing pattern spaced 125 s apart without an incoming los all-zeros/ones pattern will cause an los state to be cleared. this recovery applies to both internal and external los failure causes. the device will report this condition to the microprocessor interface ( rhslos , rhslosd , rhslosm, 0x1b, 0x0a, 0x13 ).
agere systems inc. 25 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer receive direction overview (continued) loopback select logic the device can be configured to loopback the transmit sts-3/stm-1 (au-4) ( ths2rhslb = 1 , 0x55 ) or accept the local sts-3/stm-1 (au-4) signal ( ths2rhslb = 0). while in the loopback mode, the rhsoof , rhslof , and rhslos ( 0x1b ) state bits are inhibited from causing an alarm indication signal (ais) from being generated on the sts1/au-3 output signals. rsts-3/stm-1 (au-4) frame synchronous descrambling (sonet/sdh) the device will descramble the received sonet/sdh data (minus the first row of soh) according to the frame synchronous descrambling polynomial; specifically: f(x) = 1 + x 6 + x 7 . under software control, frame descrambling can be disabled ( rhsdscr = 1 , 0x55 ). toac drop this channel drops all of the transport overhead bytes from the sts-3/stm-1 (au-4) signal. (see rtoac in the maintenance functions section, page 44, for more details (rtoacclko, rtoacsynco, rtoacdatao)). b1, b2, and b3 checking the device will monitor the incoming b1, b2, and b3 values for errors. the error counts will be latched when the latch_cnt signal transitions from a low to a high ( rhsb1ecnt[15:0] , rhsb2ecnt[17:0] , rhsb3ecnt[3?1][15:0], page 1 - 0x8d?0x8e, page 1 - 0x8f?0x91, page 1 - 0x92?0x97 ). these counters will either count bit or block errors ( bitblockcnt, 0x34 ). monitoring functions the following transport overhead and path overhead bytes are monitored for failures or changes in states ((j0, z0-2, z0-3, f1, k1k2 (aps bytes), s1, m1), (j1,c2, g1, f2, h4, z3, z5)). the bit error rate of the incoming sts-3/ stm-1 (au-4) signal is calculated to create signal fail and signal degrade indicators. (see maintenance functions disabled during failure conditions in the maintenance functions section, page 28, for more details.) pointer interpretation the device will evaluate the current pointer state for the normal state, path ais (pais) state, or loss-of-pointer (lop) conditions, as well as pointer increments and decrements (that are counted in rptr_inc[3?1][10:0] and rptr_dec[3?1][10:0] counters ( 0x98?0xa3 ), respectively). the current pointer state ( rlop[3?1 ], rpais[3?1], 0x1c ) and any changes in pointer condition ( rlopd[3?1] , rlopm[3?1] , rpaisd[3?1] , rpaism[3?1], 0x0b, 0x14 ), are reported to the control system. when the device is receiving a concatenated sig- nal (stm-1(au-3)), the rconcatmode, 0x55 bit must be set for the concatenation state machines ( concat_state[3?2][1:0], 0x1c, 0x1d ) on ports 2 and 3 to contribute to pointer evaluation. this state machine implements the pointer interpretation algorithm described in ets 300 417-1-1: january 1996 - annex b. the number of consecutive conditions for invalid pointer and invalid concatenation indication are programmable with a range 8?10 ( cntcip_ici[1:0], 0x5f ).
26 26 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer receive direction overview (continued) data demultiplex and conversion (au-4 mode only) the device will demultiplex the sts-3/stm-1 (au-4) signal into three sts-1/au-3 signals, respectively. in the au-4 mode, a conversion between the au-4 payload format and the au-3 payload format is performed. this requires the location of the j1 byte to be known, while this is not the case in the sts-3 mode, where the high- speed signal is byte demultiplexed and no format conversion occurs. sts-1/au-3 output byte control the output overhead bytes are controlled in one of four ways: 1. errors can be inserted. 2. values from the high-speed sts-3/stm-1 signal can be copied or set to the byte default. 3. values can be inserted under software control. 4. values can be inserted under hardware control. table 9 specifies the specific control allowed for each overhead byte. table 18 in the maintenance functions sec- tion provides details for selecting each control mode. 1.error insert. 2.input pass or default value. 3.software overwrite. 4.copy of the selected byte from the incoming stm-1 (au-4) frame; otherwise, the bytes pass without being changed (poh can start anywhere within the spe). 5.hardware overwrite. note: x = don?t care (payload). b1 and b2 generate the b1 and b2 values of the outgoing sts-1/au-3 signal are calculated. an error can be inserted into the b1 and b2 values on a per sts-1/au-3 basis ( rb1errins[3?1], rb2errins[3?1], 0x63 ). table 9. sts-1/au-3 format and overhead control summary transport overhead payload col. 1 col. 2 col. 3 col. 4 col. 5?90 row 1 a1 a2 1 j0 3 j1 4 x row 2 b1 1 e1 2 f1 2, 3 b3 x row 3 d1 2 d2 2 d3 2 c2 4 x row 4 h1 1, 4 h2 1, 4 h3 4 g1 4 x row 5 b2 1 k1 1, 3 k2 1, 3 f2 4 x row 6 d4 2 d5 2 d6 2 h4 4 x row 7 d7 2 d8 2 d9 2 z3 4 x row 8 d10 2 d11 2 d12 2 z4 x row 9 s1 2 m0 1, 5 e2 2 z5 4 x
agere systems inc. 27 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer receive direction overview (continued) sts-1/au-3 output scramble the device allows scrambling of the output signals on a per-output basis ( rlsscr[3?1], 0x57 ). output selection logic the demultiplexed signals can be routed to any output port or can be multicast to more than one port. the control bits ( rsel[3?1][1:0], 0x56 ) allow this to occur under software control. see table 10. output data formatter the device outputs one clock at 19.44 mhz, one j0 time signal, an 8-bit data bus, and an odd/even ( rplsparoeg, 0x57 ) parity bit. the bus can be shared with up to three other devices. each device determines its time slot using the j0 time signal. the byte coincident with the j0 time sync signal is always available for device number 1. subsequent bytes are available for device 2, device 3, and then device 1 again. the sense of the 19.44 mhz output clock can be inverted under user control ( rlsclkinv, 0x57 ). maintenance functions maintenance functions are associated with monitoring signals and conditions in the device. this section is divided into a common section, a transmit section, and a receive section. table 10. sts-1/au-3 output select control rsel [3?1][1:0] output 00 (0) sts-1/au-3 #1 receive 01 (1) sts-1/au-3 #2 receive 10 (2) sts-1/au-3 #3 receive 11 (3) undefined
28 28 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer maintenance functions (continued) maintenance functions disabled during failure conditions several maintenance functions are disabled during failure conditions. these are listed in the following table. event and status information will be disabled and all bip and far-end bit error (febe) counters will be held at 0. common maintenance and control functions the common section addresses maintenance functions that are common to both directions. device reset the device will provide a device reset function ( rstctl, 0x04 ). this device reset will be initiated by a unique input signal or by a command received through the control interface. a device reset will set all maintenance and control registers to their default values. a device reset is service affecting. note: this signal must toggle from 0 1 0. composite service request the device will provide a summary of the device monitoring conditions ( int, 0x00 ). mask bit operation mask bits will only inhibit the contribution of the event or delta bit contributing to the interrupt. the event or delta bits will not be cleared if the corresponding mask bit is cleared. delta and event bits clear-on-read. table 11. monitors disabled during failure conditions direction failure monitors disabled transmit tiloc (0x19) transmission path and all monitors dis- abled tlsoof[3?1] and tlsoof_aisinh[3?1] or tlslof[3?1] and tlslof_aisinh[3?1] (0x19, 0x37, 0x39, 0x3b) tlsb1ecnt[3?1][15:0], tlsb2ecnt[1][17:0], tlsb2ecnt[3?2][15:0] (page 1 - 0x80?0x8c) rhslos or rhslof or rhsoof (0x1b) sfebe and pfebe (au-4 mode only) insert (value set to 0) receive riloc and rriloc_aisinh ( 0x1b, 0x58 ) transmission path and all monitors dis- abled rhslos and rrhslos_aisinh or rhslof and rrhslof_aisinh or rhsoof and rrhsoof_aisinh (0x1b, 0x58) j0z0mon, f1mon, apsmon, k2mon, lrdimon, laismon, rhssf, rhssd, rhsb1ecnt[15:0], rhsb2ecnt[16:0], rsfebecnt[7:0], rpfebecnt[3?1][15:0], and all path monitoring functions (0x1b, 0xa6?0xac, 0x8e) ( rpais[3:1] or rlop[3:1] ) and paislop_aisinh (0x1c, 0x57) all path monitoring functions: j1, c2, b3, g1, f2, h4, z3, z5
agere systems inc. 29 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer maintenance functions (continued) common maintenance and control functions (continued) device version and device id number the device will have a version number ( devver[7:0], 0x03 ). the version increments each time the device func- tionality is changed, from the controller?s perspective. the device id ( devid[15:0], 0x01?0x02 ) is a fixed pattern used to identify the device by software. scratch byte the device will provide a 1-byte scratch register for the control interface to verify write capability to the device ( scratch[7:0], 0x06 ). multibyte registers if a read value parameter register requires more than 8 bits, the device must prevent the value from changing between 8-bit read commands. in these cases, the controller reads the lowest address byte first and transfers the higher address bytes to a holding register where the value is held until the controller reads them. similarly, if a multibyte writable register is implemented, the controller writes the lowest address byte first, which is stored in a holding register until the controller writes the highest address byte, and then all of the bytes take effect. to simplify device design, the controller reads or writes all of the bytes of a multibyte register before reading or writ- ing other registers so that the holding registers may be shared among all multibyte registers. this read/write oper- ation is valid on all multibyte registers not controlled by the latch_cnt, 0x04 bit. update counter control for performance monitoring purposes, there are a number of bip, febe, and pointer interpreter increment/decre- ment error counters in the receive/transmit section. all of these internal counters are comprised of a running error counter and a hold register that present stable results to the microprocessor. the counts in all of the running counters are latched to the hold registers when latch_cnt, 0x04 is written from a logic 0 to a logic 1. this zeros all of the running counters. the results are held to be read by the microprocessor. all of the internal counters have the ability to store more than 1 second?s worth of counts, so as long as the latch_cnt occurs every second, or faster, no counts will be lost. in case this doesn?t happen, all of the running counters will hold their maximum value rather than roll over to 0. the following counters 1 are affected by latch_cnt : tlsb1ecnt[3?1][15:0], 0x08?0x85 tlsb2ecnt[1][17:0], 0x86?0x88 tlsb2ecnt[3?2][15:0], 0x89?0x8c rhsb1ecnt[15:0], 0x8d?0x8e rhsb2ecnt[17:0], 0x8f?0x91 rhsb3ecnt[3?1][15:0], 0x92?0x97 rptr_inc[3?1[10:0], 0x98?0x9d rptr_dec[3?1][10:0], 0x9e?0xa3 rsfebecnt[17:0], 0xa4?0xa6 rpfebecnt[3?1][15:0], 0xa7?0xac 1 all addresses for these counters are in page 1 registers.
30 30 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer maintenance functions (continued) common maintenance and control functions (continued) bit or block count the device allows all counters, except the pseudorandom error counter, to either count the actual number of bit errors or the number of blocks (a block equals one frame) that contain an error ( bitblockcnt, 0x34 ). the section and path febe counters count the actual number of bit errors or the number of blocks that contain an error ( febebitblockcnt, 0x34 ). transmit functions the transmit section addresses maintenance functions that are unique to the transmit direction. parity (b1, b2, b3) the device will perform a bit interleaved bip-8 parity (b1) calculation and will write these bits into the b1 section overhead byte. the device will perform a bit interleaved bip-24 parity (b2) calculation and will write these bits into the b2 line overhead byte. the device will perform a bit interleaved bip-8 parity (b3) calculation and will write these bits into the b3 path overhead byte (au-4 mode only). the device can perform a b1 ( thsb1errins, 0x4c ), b2 ( thsb2errins[3?1], 0x4c ), and b3 ( thsb3errins, 0x4c ) parity byte inversion via microprocessor control. a1, a2 error enable the device will allow, under software control, from 1 to 32 continuous frames to have errored a1a2 patterns in the outgoing frame ( ta1a2errins[4:0], 0x4d and ta1a2erren, 0x04 ). section trace/growth byte insert (j0/z0) the device inserts the data written into tj0dins[7:0], 0x3f, tz02dins[7:0], 0x40, and tz03dins[7:0], 0x41 into the outgoing j0/z0 bytes. fault location insert (f1) via microprocessor control of tf1ins, 0x3e and tf1dins[7:0], 0x42 , data information may be inserted into the outgoing f1 byte. direct microprocessor insert has higher priority than the toac insert control bit ( ttoac_f1[1:0], 0x51 ). sync status byte insert (s1) via microprocessor control of ts1ins, 0x3e and ts1dins[7:0]0x45 , data information may be inserted into the outgoing s1 byte. direct microprocessor insert has higher priority than the toac insert control bit ( ttoac_z1[1:0], 0x51 ). automatic protection switch (aps) insertion (k1[7:0], k2[7:3]) the device writes the k1 and k2 bytes into the transmit k1 and k2 overhead bytes ( tapsins[12:0], 0x43, 0x44 ). the k1 and k2[7:3] bits will only change when both values are valid. the tapsins[4:0], 0x44 byte is the trigger for updating the aps bytes in the outgoing frame.
agere systems inc. 31 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer maintenance functions (continued) transmit functions (continued) aps babbling test control setting the tapsbableins, 0x4d register, via microprocessor control, forces the aps bytes (k1[7:0], k2[7:3]) to an inconsistent state. line remote defect indication (rdi-l) insertion (k2[2:0] = 110) the device will write line rdi into the data signal using the following equation: tlrdiint =(riloc and triloc_lrdiinh ) or (rhslos and trhslos_lrdiinh ) or (rhsoof and trhsoof_lrdiinh ) or (rhslof and trhslof_lrdiinh ) or (rlaismon and trlaismon_lrdiinh ) or (rhssf and trhssf_lrdiinh ); (see 0x1a, 0x1b, 0x1d, and 0x4a.) hardware insert of line rdi will occur when tlrdiint, 0x1a is active and the software insert control bit ( tlrdiinh, 0x4a ) is disabled. user-provided data ( tk2ins[2:0], 0x43 ) will be inserted into the k2[2:0] bits in the sts-3/stm-1 (au-4) frame when tlrdiinh = 0. the insertion of line rdi consists of writing the pattern 110 into the three lsbs of the k2 loh byte. unequipped and ais generation (automatic/manual) line ais or au4-ais or tug-3 ais can be generated automatically by the hardware under certain failure condi- tions or via microprocessor control only. this is accomplished with the following equations and control signals: failure[3?1] = (( tlsoof[3?1] and tlsoof_aisinh[3?1] ) or ( tlslof[3?1] and tlslof_aisinh[3?1] )) h4ptrmis[3?1] = (( tlsh4mis[3?1] and tlsh4mis_aisinh[3?1] ) or ( tlsptrmis[3?1] and ( tlsptrmis_aisinh[3?1] )) and sts1_au4 ; au-4 mode only lais[3?1] = tls_laisins[3?1] or failure[3?1] or h4ptrmis[3?1]; au4aisgen = lais1 and lais2 and lais3; (see 0x1a, 0x37, 0x39, 0x3b.) each alarm contribution that can cause ais generation can be selectively inhibited . line ais is generated in the sts-3 mode per sts-1 input when the appropriate failure[3?1] or tls_laisins[3?1] (software enable) sig- nals are active. (line overhead and the entire payload is set to an all-ones pattern.) in this mode, the h4ptrmis[3?1] contribution will always be 0. au4-ais generation will set all h1, h2, h3, and payload bytes to an all-ones pattern in the output stm-1 (au-4) signal. tug-3 ais generation will force all the data in the selected tug-3 signal to be set to an all-ones pattern. in the sts-3 mode, an unequipped signal can be generated for any sts1 input under software control ( tls_unequip[3?1], 0x3b, 0x39, 0x37 and (h1 = 0110ss00 and h2 = 00000000)) and the selected payload is set to 0). in au-4 mode, the h1 and h2 bytes will not change from their default values and the entire payload will be set to 0. the ss bits will be set to the value written into register bits ( tss[1:0], 0x3e ). ais generation has higher priority than unequipped signal generation.
32 32 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer maintenance functions (continued) transmit functions (continued) h1 and h2 corruption setting the th1h2crupen[3?1], 0x4e, register, via microprocessor control, allows the outgoing h1 and h2 val- ues to be corrupted for each sts-1 channel. either an invalid pointer or a continuous new data flag can be inserted (th1h2crupporndf, 0x4e). loss-of-transmit clock or loss-of-frame sync the device will detect a loss-of-transmit clock condition for the clock input in the transmit direction. also, the device was designed to detect a loss-of-frame sync for the frame sync input signal (note, the loss-of-frame sync (tilof) feature is not supported in version 3 of the device). the state of tiloc and tilof (0x19 ) along with any changes to tilocfd and tilocfm (0x07 and 0x10) will be reported to the control system. transmit clock frequency provisioning the device must be provisioned ( thsclktype[1:0], 0x3c ) with the speed (155.52 mhz?bit, 38.88 mhz? nibble, 19.44 mhz?byte) of the transmit clock. this information is needed to set the internal clock divider circuitry and determine valid output port modes (e.g., a byte clock input cannot support a serial output port at 155.52 mbits/s).
agere systems inc. 33 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer maintenance functions (continued) transmit functions (continued) section far-end bit error (sfebe) the device will insert sfebe in the transmitted m1 byte whenever there are bit errors in the received b2 bytes. this function can be inhibited ( tsfebeinh , 0x3e ) and the default value inserted, either all ones (sdh) or all zeros (sonet). the device can insert a continuous error into the m1 byte under user control ( tsfebeeins, 0x4d ). sfebe will be inserted into the m1 byte as defined in figure 3. 5-5295(f) figure 3. sfebe location the values for sfebe are summarized in table 12. table 12. sfebe values section or line febe number of b2 bit errors in the receive signal 00000000 0 (no errors) 00000001 1 00000010 2 . . . . . . 00010111 23 00011000 24 00011001 no errors . . . 11111110 11111111 (sdh) 00000000 (sonet) section febe not supported (no errors) z2-1 z2-2 m1 23 (msb) 0 (lsb) 0 (lsb) 7 (msb) section febe
34 34 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer maintenance functions (continued) transmit functions (continued) path - trace byte (j1)?au-4 mode only the device will continuously insert a 64-byte sequence ( tj1dins[64?1][7:0], 0x80?0xbf ) into the outgoing stm-1 (au-4) signal when the tj1ins signal is active; otherwise, all zeros will be inserted into this byte. path - signal label byte (c2)?au-4 mode only the device will allow data to be inserted into the outgoing c2 byte under software control ( tc2dins[7:0], 0x46 ). path - g1 status byte (pfebe (reicnt))?au-4 mode only the g1 byte contains the pfebe (b3 errors) as shown in table 13. the device will insert pfebe in the transmitted g1 byte whenever there are bit errors in the received b3 byte. this function can be inhibited ( tpfebeinh, 0x3e ) and the default value inserted, either all ones (sdh) or all zeros (sonet). the device can insert a continuous error into the g1 pfebe[3:0] byte under user control ( tpfebeeins, 0x4d ). the values for pfebe are summarized in table 14. table 13. g1 byte?au-4 mode only msb (7) 654 3 21lsb (0) pfebe[3:0] valid values (0 to 8) all others indicate no errors rdi-p 111 (sdh) or 000 (sonet) table 14. pfebe values section or line febe number of b3 bit errors in the receive signal 0000 0 (no errors) 0001 1 0010 2 . . . . . . 0111 7 1000 8 1001 no errors . . . 1111
agere systems inc. 35 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer maintenance functions (continued) transmit functions (continued) path - g1 status byte (rdi-p)?au-4 mode only the g1 byte contains the rdi-p bit as shown in table 13. path rdi is inserted automatically under hardware control. each failure contribution can be excluded from the gen- eration equation by setting the appropriate inhibit bit. tprdiint =(( riloc and triloc_prdiinh ), 0x4b , or ( rhslos and trhslos_prdiinh ), 0x4b , or ( rhsoof and trhsoof_prdiinh ), 0x4b , or ( rhslof and trhslof_prdiinh ), 0x4b , or ( rlaismon and trlaismon_prdiinh ), 0x4b , or ( rpais1 and trpais1_prdiinh ), 0x4b , or ( rlop1 and trlop1_prdiinh ), 0x4b , or tprdiins (software insert)); (see 0x1a, 0x1b, 0x4b.) prdi can be forced, via microprocessor control, by setting tprdiins to a logic 1. path - user channel byte (f2)?au-4 mode only via microprocessor control of the ( tf2dins[7:0], 0x47 ), data information may be inserted into the outgoing f2 byte. path - growth byte (z3)?au-4 mode only via microprocessor control of the ( tz3dins[7:0], 0x48 ), data information may be inserted into the outgoing z3 byte. path - tandem connection byte (z5)?au-4 mode only via microprocessor control of the ( tz5dins[7:0], 0x49 ), data information may be inserted into the outgoing z5 byte. pseudorandom test pattern insert?au-4 mode only a pseudorandom test sequence can be inserted into any selected ( tstgen_psel[1:0], 0x4e ) tug-3 within the au-4 signal. the pattern can be selected from the following two equations: q23 + q17 + 1 or q15 + q14 + 1 ( tpat23or15, 0x4e ). a one shot is provided to inject eight (8) errors into the selected pseudorandom sequence ( tstgene8ins, 0x04 ). a value of zero in the tstgen_psel[1:0] register disables this function.
36 36 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer maintenance functions (continued) transmit functions (continued) output offset the device will output the sts-3/stm-1 (au-4) frame a programmable number of clock cycles from the input frame sync. these registers allow movement of the output frame with a granularity of one high-speed clock cycle. the values programmed in ( tlbitcnt[2:0], tlsts1cnt[1:0], tlcolcnt[6:0] , tlrowcnt[3:0], 0x53, 0x54 ) must be within the valid ranges for the mode selected (see table 15). see table 56 on page 77 for more details. transmit transport overhead access channel (ttoac) a transport overhead access channel (toac) is provided on-chip to provision the toh portion of the outgoing sdh or sonet frame. the toac consists of the following signals: a 5.184 mhz clock signal, sourced by the device ( ttoacclko, ttoac_clkinv ). a 5.184 mbits/s data signal received by the device in the transmit direction ( ttoacdatai ). an 8 khz synchronization signal ( ttoacsynco ), sourced by the device. the sync signal is normally low; during the last clock period of each frame coincident with the least significant bit of the eighty-first byte or during the first clock period of each frame coincident with the most significant bit of the first byte, the sync signal is high ( ttoacsa1orend, 0x4f ). an inhibit signal is provided through the control interface to place the clock and sync signals in a high-impedance state ( ttoacinh, 0x4f ). the data signal is partitioned into frames of 81 bytes. the frame repetition rate is 8 khz. each byte consists of 8 bits that are received most significant bit first. the msb of the first byte of each frame contains an odd/even parity bit over the 648 bits of the previous frame. the remaining 7 bits of this byte are not specified. bytes shown in table 16 summarize the access capabilities of the transmit toac. bytes indicated in bold type are not specified in the standard, but are labeled here for clarity. x symbols indicate don?t cares. table 15. value offset load values mode tlbitcnt[2:0] tlsts1cnt[1:0] tlcolcnt[6:0] tlrowcnt[3:0] bit 0?7 0?2 0?89 0?8 nibble 0?1 0?2 0?89 0?8 byte 0 0?2 0?89 0?8 table 16. transport overhead byte access?transmit direction oh ptyxxxxxxxx x b1-2 b1-3 e1 e1-2 e1-3 f1 f1-2 f1-3 d1 d1-2 d1-3 d2 d2-2 d2-3 d3 d3-2 d3-3 xxxxxxxxx xxxx k1-2 k1-3 x k2-2 k2-3 d4 d4-2 d4-3 d5 d5-2 d5-3 d6 d6-2 d6-3 d7 d7-2 d7-3 d8 d8-2 d8-3 d9 d9-2 d9-3 d10 d10-2 d10-3 d11 d11-2 d11-3 d12 d12-2 d12-3 s1 z1-2 z1-3 z2 z2-2 x e2 e2-2 e2-3
agere systems inc. 37 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer maintenance functions (continued) transmit functions (continued) oh parity an event indication is provided at the control interface if an overhead parity error occurs. odd/even parity is checked ( ttoac_oepmon , ttoac_perrm, ttoac_perre, 0x4f, 0x10, 0x07 ) . d1?d3, d4?d12, e1, e2, f1, z1, z2 overhead bytes table 17 summarizes the insertion options for the specified overhead bytes. the device allows (1) the default value for unused sdh or sonet bytes to be inserted, or (2) the transmit toac values to be inserted, or (3) the received sts-1/au-3 value to be inserted into the outgoing sts-3 frame. table 17. ttoac control bits overhead bytes control bits 1 1. see address 0x50, 0x51 for control bits. values 00 (default) or 11 01 10 d1?d3 ttoac_d1to3[1:0] sdh (1s) or sonet (0s) default values ttoac data pass through associated sts-1/au-3 data d4?d12 ttoac_d4to12[1:0] e1 ttoac_e1[1:0] e2 ttoac_e2[1:0] f1 ttoac_f1[1:0] s1, z1-2, z1-3 ttoac_z1[1:0] z2, z2-2 ttoac_z2[1:0] b1-2, b1-3 ttoac_ins[1:0] sdh (1s) or sonet (0s) default values ttoac pass through associated sts-1/au-3 data e1-2, e1-3 f1-2, f1-3 d1-2, 3 to d3-2, 3 k1-2, k1-3 k2-2, k2-3 d4-2, 3 to d12-2, 3 e2-2, e2-3
38 38 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer maintenance functions (continued) receive functions a number of the receive maintenance functions require a continuous n times detection (cntd) of a signal to change an alarm status. all of these continuous n times detect signals require not only that the monitored signal be consistent for n consecutive frames, but also that the frame bytes, a1 and a2, be error free for all n frames before the status can be updated. if there are any errors in the framing pattern, then the consecutive n times detection counters must be reset to 0. n can range from 3 to 15. there is also a signal ( cntdb1sel, 0x5f ) that will cause these continuous n times detection counters to be reset to 0 if there are any errors in the received b1 byte. continuous n times detect b1 error reset enable the following cntd monitors are affected by this control bit ( cntdb1sel ): 1. ais-l (k2[2:0] = 111) 2. rdi-l (k2[2:0] = 110) 3. k2mon (k2[2:0]) 4. apsmon (k1[7:0], k02[7:3]) receive loss of clock the device will detect a receive loss-of-clock ( riloc, 0x1b ) condition for the clock input and notify the control sys- tem of any changes to this condition ( rilocd, 0x0a, and rilocm, 0x13 ). insertion of line ais (automatic/manual) the device will write line ais into each sts-1/au-3 output signal if either the appropriate alarms occur or the soft- ware insert bit is active. lais_common = (( riloc and rriloc_aisinh ) or ( rrhsoof and rhsoof_aisinh ) or ( rhslof and rrhslof_aisinh ) or ( rhslos and rrhslos_aisinh ) or ( laismon and rrlaismon_aisinh )); (see 0x1b, 0x58.) if ( rlaisins[3?1] = 1 or lais_common = 1), then insert line ais on the selected output. when a riloc condition exists, the transmit clock is used to generate the line ais signal downstream, if possible. insertion of path ais (automatic) the device will write path ais into each sts-1/au-3 output signal if the appropriate alarms occur. pais_common[3?1] = ( (pais[3?1] or lop[3?1] ) and paislop_aisinh ) if (pais_common[3?1] = 1), then insert path ais on the appropriate output. (pais consists of writing all ones into the h1, h2, h3 bytes, and into the entire payload.) b1 bip-8 parity the device will perform b1 (bip-8) calculation and error checking in the receive path. the device will allow access to the b1 errored bit/block (one block is equal to one frame) count ( bitblockcnt, 0x34, rhsb1ecnt[15:0], 0x8d-0x8e ). this counter will update when latch_cnt transitions from a logic 0 to a logic 1.
agere systems inc. 39 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer maintenance functions (continued) receive functions (continued) b2 bip-24 parity the device will perform b2 (bip-24) calculation and error checking. the device will allow access to the b2 errored bit/block (one block is equal to one frame) count ( bitblockcnt, 0x34, rhsb2ecnt[16:0], page 1 - 0x8f? 0x91) . this counter will update when latch_cnt, 0x04 transitions from a logic 0 to a logic 1. signal degrade ber algorithm a signal degrade state and change of state indication will be provided to the control interface ( rhssd, rhssdd, rhssdm, 0x1b, 0x0a, 0x13 ). this bit error rate algorithm can operate on either b1 or b2 errors ( sdb1b2sel, 0x83 ). signal degrade is declared when sdlset[3:0], page 2 - 0x83 or more bit errors in sdnsset[18:0], page 2 - 0x8e?0x90 and frames occur sdmset[7:0], page 2 - 0x84 times out of sdbset[11:0], page 2 - 0x85?0x86 blocks (one block is equal to one measurement period of sdnsset[18:0] frames), and it is removed when less than sdlclear[3:0], page 2 - 0x8a bit errors in sdnsclear[18:0], page 2 - 0x87?0x89 frames occur sdm- clear[7:0], page 2 - 0x8b times out of sdbclear[11:0], page 2 - 0x8c?0x8d blocks. the above algorithm can detect bit error rates from 1 x 10 ?3 to 1 x 10 ?9 . signal fail ber algorithm a signal fail state and change of state indication will be provided to the control interface ( rhssf, rhssfd, rhssfm, 0x1b, 0x0a, 0x13 ). this bit error rate algorithm can operate on either b1 or b2 errors ( sfb1b2sel, page 2 - 0x91 ). signal fail is declared when sflset[3:0], page 2 - 0x91 or more bit errors in sfnsset[18:0], page 2 - 0x8e?0x90 frames occur sfmset[7:0], page 2 - 0x92 times out of sfbset[11:0], page 2 - 0x93?0x94 blocks (one block is equal to one measurement period of sfnsset[18:0] frames), and it is removed when less than sflclear[3:0], page 2 - 0x98 bit errors in sfnsclear[18:0], page 2 - 0x96?0x98 frames occur sfmclear[7:0] , page 2 - 0x99 times out of sfbclear[11:0] page 2 - 0x9a?0x9b blocks. the above algorithm can detect bit error rates from 1 x 10 ?3 to 1 x 10 ?9 . section trace (j0, z0-2, z0-3) byte monitoring the device will monitor the section trace bytes ( rj0mon[7:0] , rz02mon[7:0], rz03mon[7:0], rcdrloc, 0x1e, 0x1f, 0x20, 0x1b ) on the receive input. a new section trace value will be detected after cntdj0z0[3:0], 0x5a and consecutive consistent occurrences of a new pattern in the section trace overhead bytes. any changes to these bytes will be reported to the control system ( rj0z0mond, rj0z0monm, 0x0c, 0x15 ). fault location monitoring (f1mon) the device will monitor the fault location byte ( rf1mon0[7:0], 0x21 ) on the receive input. a new fault location state will be detected after cntdf1[3:0], 0x5a consecutive consistent occurrences of a new pattern in the f1 overhead byte. the device will also maintain a history of the previous valid f1 byte ( rf1mon1[7:0], 0x22 ). any changes to this byte will be reported to the control system ( rf1mond, rf1monm, 0x0c, 0x15 ). automatic protection switch (aps) monitoring the device will monitor the k1 byte and the k2 byte (5 msbs only) on the input side of the device receive path ( rapsmon[12:0], 0x23, 0x24 ). after cntdaps[3:0], 0x5b consecutive consistent occurrences of new k1 and k2 bytes, the device will notify the control system ( rapsmond, rapsmonm, 0x0b, 0x14 ).
40 40 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer maintenance functions (continued) receive functions (continued) aps babbling monitor the device will monitor the aps bytes (k1[7:0], k2[7:3]) in the receive direction and report to the control interface ( rapsbablee , rapsbablem, 0x0c, 0x15 ) when the k1 bytes are inconsistent. inconsistent aps bytes are defined as cntdapsframe[3:0] , 0x5c (default = 12) successive frames, starting with the last frame containing previously consistent code, where no cntdaps[3:0], 0x5b (default = 3) consecutive frames contain identical aps bytes. line ais (ais-l) monitoring the device will monitor line ais on the receive input ( rlaismon, 0x1d ). line ais will be detected after cntdk2[3:0], 0x5b consecutive occurrences of the ais-l pattern (xxxxx111) in the k2 overhead byte. any changes to this byte will be reported to the control system ( rlaismond , rlaismonm, 0x0c, 0x15 ). line remote defect indication (rdi-l) monitoring the device will monitor an rdi-l condition on the receive input ( rlrdimon, 0x1d ). a line rdi condition will be detected after cntdk2[3:0] consecutive occurrences of the line rdi pattern (xxxxx110) in the k2 overhead byte. any changes to this byte will be reported to the control system ( rlrdimond , rlrdimonm, 0x0c, 0x15 ). k2 byte monitoring the device will monitor the k2 byte (3 lsbs only) on the input side of the receive direction ( rk2mon[2:0], 0x23 ). after cntdk2[3:0], 0x5b consecutive consistent occurrences of new k2 bits, the device will notify the control sys- tem ( rk2mond , rk2monm, 0x0b, 0x14 ). sync status (s1) byte monitoring the device will monitor the sync trace byte ( rs1mon[7:0], 0x25 ) on the receive input. a new sync trace value will be detected after cntds1[3:0], 0x5c consecutive consistent occurrences of a new pattern in the overhead bytes. any changes to this byte will be reported to the control system ( rs1mond, rs1monm, 0x0c, 0x15 ). section febe (m1) monitoring the device will monitor a section febe condition (m1) on the receive input. the device will allow access to the section febe errored bit/block (one block is equal to one frame) count ( febebitblockcnt, 0x34 , rsfebecnt[17:0], page 1 - 0x34, 0xa4, 0xa6 ). this counter will update when latch_cnt transitions from a logic 0 to a logic 1. au-4 npi (null pointer indication) monitoring the device will monitor the three npi values in the incoming stm-1(au-4) signal. when five consecutive mis- matches occur (any one of the three npi values are in error) separated in time by 125 s, the device will declare an npi mismatch condition. an npi match condition is declared when two consecutive matches occur (all three npi values match), separated in time by 125 s. the delta, mask, and state bits are rhsnpimisd , rhsnpimism , rhsnpimis, 0x0d, 0x16, 0x1d , respectively.
agere systems inc. 41 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer maintenance functions (continued) receive functions (continued) stm-1(au-4) h4 multibyte monitor the device will monitor the path h4 byte for correct multibyte sequence. each time the expected value mismatches with the received value, an event indication is set. when a mismatch occurs, the device accepts the new value plus 1 as the expected value for the next frame. the event and mask bits are rhsh4mise , rhsh4mism, 0x0d, 0x16 . path trace byte (j1) monitoring the device will monitor the path trace byte ( rj1mon[64?1][7:0], 0xc0?0xff ) on the receive input. only one j1 byte can be monitored ( j1pselmon[1:0], 0x56 ) out of the three possible j1 bytes. the device will store a 64-byte sequence and declare a mismatch each time the incoming value does not agree with the stored value ( rj1mise, rj1mism, 0x0c, 0x15 ). path signal label (c2) monitoring the device will monitor the c2 bytes on the receive input ( rc2mon[3?1][7:0], 0x28, 0x27, 0x26 ). after cntdc2[3:0], 0x5d consecutive consistent occurrences of a new c2 byte, the device will notify the control system ( rc2mond[3?1], rc2monm[3?1], 0x0d, 0x16 ). path febe (g1) byte error count the device will monitor for a path febe condition (g1[7:4]) on the input signal. the device will allow access to the path febe errored bit/block (one block is equal to one frame) count ( febebitblockcnt , rpfebecnt[3?1][15:0], 0x34, 0xa7?0xac ). these counters will update when latch_cnt, 0x04 transitions from a logic 0 to a logic 1. path rdi (path yellow (g1[3] or enhanced failure code (g1[3:1]))) the device will monitor the g1 bytes for path yellow condition or for an enhanced failure code ( rrdi_mpyorefc, 0x55 ) on the receive input ( rrdip[3?1][2:0], 0x32, 0x33 ). after cntdg1[3:0], 0x5d consecutive consistent occurrences of a new g1 value, the device will notify the control system ( rrdipe[3?1], rrdipm[3?1], 0x16 ). path user channel (f2) monitoring the device will monitor the f2 byte ( rf2mon[3?1][7:0], 0x29, 0x2a, 0x2b ) on the receive input. a new value will be detected after cntdf2[3:0], 0x5e consecutive consistent occurrences of a new pattern in the overhead bytes. any change to this byte will be reported to the control system ( rf2mond[3?1], rf2monm[3?1], 0x0e, 0x17 ). path growth byte (z3) monitoring the device will monitor the z3 bytes ( rz3mon[3?1][7:0], 0x2c, 0x2d, 0x2e ) on the receive input. a new value will be detected after cntdz3[3:0], 0x5e consecutive consistent occurrences of a new pattern in the overhead bytes. any change to this byte will be reported to the control system ( rz3mond[3?1], rz3monm[3?1], 0x0e, 0x17 ). path tandem connection byte (z5) monitoring the device will monitor the z5 bytes ( rz5mon[3?1][7:0], 0x31, 0x30, 0x2f ) on the receive input. a new value will be detected after cntdz5[3:0], 0x5f consecutive consistent occurrences of a new pattern in the overhead bytes. any change to this byte will be reported to the control system ( rz5mond[3?1], rz5monm[3?1], 0x0f, 0x18 ).
42 42 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer maintenance functions (continued) receive functions (continued) test pattern drop (au-4 mode only) the device will monitor a pseudorandom pattern ( rpat23or15, 0x60 ) on a per tug-3 basis ( rtstdrp_psel[1:0], 0x60 ). the drop logic will provide an out-of-sync indication ( rtstdrp_oos, 0x60 ) and an error count ( rtstdrp_ecnt[7:0], 0x61 ). this counter will hold at its maximum value and is not affected by the latch_cnt, 0x04 signal. the detector will transition to the in-sync-state after 32 consecutive matches occur. the detector will transition from the in-sync-state to the out-of-sync state if 32 consecutive errors are detected. sts-1/au-3 byte error insert or overwrite control this section summarizes the output error and overwrite capabilities on a per sts1/au-3 basis. all path overhead bytes pass through from the input signal. table 18. sts-1/au-3 overhead control control signal per sts-1/ au-3 signal bytes affected/ action action ra1a2erren, ra1a2errpen[3?1], ra1a2errins[4:0] (0x05, 0x62) a1, a2 error insert if ( ra1a2erren = 0 1) then insert ra1a2errins[4:0] consecutive frame errors on the selected ports ( ra1a2errpen[3?1] ) else insert correct framing pattern. rc1dins[3?1][7:0] (0x68, 0x69, 0x6a) c1 always insert values. rb1errins[3?1] (0x63) b1 error insert 1 = insert error, 0 = insert normal value. r_e1_pass[3?1] (0x74) e1 1 = pass input data, 0 = insert default value. rf1ins[3?1] rf1dins[3?1][7:0], r_f1_pass[3?1] (0x64, 0x6b?0x6d, 0x74) f1 software or pass if ( rf1ins = 1) then insert software value ( rf1dins ) else if ( r_f1_pass = 1) then pass input data else set byte to the default value. r_d1tod3_pass[3?1] (0x75) d1 to d3 1 = pass input data, 0 = insert default value. rh1h2crupen[3?1], rh1h2crupporndf (0x64) h1, h2 error insert if ( rh1h2crupporndf = 0 and rh1h2crupen = 1) then continuously corrupt the pointer value else if ( rh1h2crupporndf = 1 and rh1h2crupen = 1) then continuously send ndf (1001) pattern else pass input data. rb2errins[3?1] (0x63) b2 error insert 1 = insert error, 0 = insert normal value. rapsbableins[3?1], rapsins[3?1][12:0] (0x66, 0x6e?0x73) k1, k2[7:3] error or software if ( rapsbableins = 1) then continuously insert a nonconsistent k1k2 value else insert software value rapsins .
agere systems inc. 43 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer maintenance functions (continued) receive functions (continued) table 18. sts-1/au-3 overhead control (continued) control signal per sts-1/ au-3 signal bytes affected/ action action rlrdiint[3?1] rtiloc_lrdiinh, rtlslof_lrdiinh[3?1] , rtlsoof_lrdiinh[3?1], rk2dins[3?1][2:0] (0x1d, 0x67, 0x6e, 0x70, 0x72) k2[2:0] automatic/ software rlrdiint[3?1] = ( tiloc and tiloc_lrdiinh ) or ( rtlslof[3?1] and rtlslof_lrdiinh[3?1] ) or ( rtlsoof[3?1] and rtlsoof_lrdiinh[3?1 ] ); 1 if (all associated inhibit signals are active) then insert software value rk2dins[3?1][2:0] else insert 110 pattern when rlrdiint[3?1] is active else insert 000 pattern. 1. software enable when all hardware inhibit signals are 1. r_d4tod12_pass[3?1] (0x75) d4 to d12 1 = pass input data, 0 = insert default value. r_s1_pass[3?1] (0x76) s1 1 = pass input data, 0 = insert default value. rsfebeinh[3?1] rsfebeerrins[3?1] (0x65) m0 automatic or error insert if ( rsfebeinh = 1) then inhibit the insertion of b2 errors and set the byte to the default value else if ( rsfebeerrins = 1) then insert an error into the output byte else output b2 errors per frame from the associated transmit input. r_e2_pass[3?1] (0x76) e2 1 = pass input data, 0 = insert default value.
44 44 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer maintenance functions (continued) receive functions (continued) receive transport overhead access channel (rtoac) a toac is provided on-chip to drop the toh portion of the incoming sdh or sonet frame. the toac channel consists of the following signals: 1. 5.184 mhz clock signal, sourced by the device ( rtoacclko, rtoac_clkinv ). 2. a 5.184 mbits/s data signal, sourced by the device ( rtoacdatao ). 3. an 8 khz synchronization signal, sourced by the device. the sync signal is normally low; during the last clock period of each frame coincident with the least significant bit of the eighty-first byte or coincident with the least significant bit of the first byte, the sync signal can go high ( rtoacs_a1orend, 0x4f ). an inhibit signal is provided through the control interface to place the clock, data, and sync signal into a high- impedance state ( rtoacinh, 0x4f ). the data signal is partitioned into frames of 81 bytes. the frame repetition rate is 8 khz. each byte consists of 8 bits that are transmitted/received most significant bit first. the msb of the first byte of each frame contains an odd/even parity bit over the 648 bits of the previous frame. the remaining 7 bits of this byte are not specified. bytes shown in table 19 summarize the access capabilities of the receive toac. bytes indicated in bold type are not specified in the standard, but are labeled here for clarity. oh parity even or odd parity can be inserted into the first bit of the msb byte ( rtoac_oepins, 0x4f ) of the toac outgo- ing frame. table 19. transport overhead byte access?receive direction oh pty a1-2 a1-3 a2-1 a2-2 a2-3 j0 z0-2 z0-3 b1 b1-2 b1-3 e1 e1-2 e1-3 f1 f1-2 f1-3 d1 d1-2 d1-3 d2 d2-2 d2-3 d3 d3-2 d3-3 h1-1 h1-2 h1-3 h2 h2-2 h2-3 h3 h3-2 h3-3 b2-1 b2-2 b2-3 k1 k1-2 k1-3 k2 k2-2 k2-3 d4 d4-2 d4-3 d5 d5-2 d5-3 d6 d6-2 d6-3 d7 d7-2 d7-3 d8 d8-2 d8-3 d9 d9-2 d9-3 d10 d10-2 d10-3 d11 d11-2 d11-3 d12 d12-2 d12-3 s1 z1-2 z1-3 z2-1 z2-2 m1 e2 e2-2 e2-3
agere systems inc. 45 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer typical uses section and line termination multiplex using the device without internal loopbacks results in a multiplex/demultiplex operation. 5-5296 (f) figure 4. line termination multiplex sts-3/stm-1 (au-4) out sts-1/au-3 out sts-3/stm-1 (au-4) in control signals transmit direction receive direction toac drop 3:1 mux logic spe generate 1:3 demux logic framer overhead transport/path monitor select/ logic multi- cast overhead monitor toac insert microprocessor local clock generation bus overhead monitor interface overhead monitor drop select add control sts-1/au-3 in control signals bus control logic
46 46 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer typical uses (continued) add/drop multiplex using the device with sts-1/au-3 internal loopbacks results in an add/drop multiplex. 5-5297 (f) figure 5. add/drop multiplex digital cross connect using the device with sts-3 internal loopback results in a digital cross connect. 5-5298 (f) figure 6. digital cross connect 3:1 mux logic overhead generate 1:3 demux logic framer transport monitor sts-3 in sts-3 out sts-1/au-3 in sts-1/au-3 out select/ multi- cast logic drop select receive direction transmit direction logic drop select logic add bus control logic 3:1 mux logic overhead generate 1:3 demux logic overhead monitor sts-1/au-3 #1 in sts-1/au-3 #2 in sts-1/au-3 #3 in framer transport monitor drop select logic sts-1/au-3 #1 out sts-1/au-3 #2 out sts-1/au-3 #3 out overhead monitor overhead monitor
agere systems inc. 47 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface overview the device is equipped with an asynchronous microprocessor interface that can operate with most commercially available microprocessors. inputs mpmux and mpmode are used to configure this interface into one of four pos- sible modes. the mpmux setting selects either a multiplexed 8-bit address/data bus (ad[7:0]) or a demultiplexed 8-bit address bus (a[7:0]) and an 8-bit data bus (ad[7:0]). the mpmode setting selects the associated set of reg- isters within the device. due to device flexibility, there are no default powerup or reset states. all read/write registers must be written by the microprocessor on system start-up to guarantee proper device functionality. the microprocessor interface can operate at speeds up to 32.768 mhz in interrupt-driven or polled modes without requiring any wait-states. microprocessor configuration modes table 20 highlights the four microprocessor modes controlled by the mpmux and mpmode inputs. table 20. microprocessor configuration modes * when the mpmode3ale input pin = 0, ale is not used to retime the incoming address. microprocessor interface pinout descriptions the mode [1?4] specific pin definitions are given in table 21. note that the microprocessor interface uses the same set of pins in all modes. table 21. mode [1?4] microprocessor pin definitions mode mpmode mpmux address/data bus generic control, data and output pin names mode 1 0 0 demuxed cs , as , ds , r/w , a[7:0], ad[7:0], int, dtack mode 2 0 1 muxed cs , as , ds , r/w , ad[7:0], int, dtack mode 3* 1 0 demuxed cs , ale, rd , wr , a[7:0], ad[7:0], int, rdy mode 4 1 1 muxed cs , ale, rd , wr , ad[7:0], int, rdy configuration device pin name generic pin name pin type assertion sense function mode 1 wr _ds ds input active-low data strobe rd _r/w r/w input ? read/write r/w = 1 for read r/w = 0 for write ale_as as input ? address strobe cs cs input active-low chip select int int output active-high interrupt rdy_dtack dtack output active-low data acknowledge ad[7:0] ad[7:0] i/o ? data bus a[7:0] a[7:0] input ? address bus
48 48 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) microprocessor interface pinout descriptions (continued) table 21. mode [1?4] microprocessor pin definitions (continued) * optional (mpmode3ale). configuration device pin name generic pin name pin type assertion sense function mode 2 wr _ds ds input active-low data strobe rd _r/w r/w input ? read/write r/w = 1 for read r/w = 0 for write ale_as as input ? address strobe cs cs input active-low chip select int int output active- high interrupt rdy_dtack dtack output active-low data acknowledge ad[7:0] ad[7:0] i/o ? address/data bus mode 3 wr _ds wr input active-low write rd _r/w rd input ? read ale_as ale* input ? address latch enable cs cs input active-low chip select int int output active- high interrupt rdy_dtack rdy output active-low ready ad[7:0] ad[7:0] i/o ? data bus a[7:0] a[7:0] input ? address bus mode 4 wr _ds wr input active-low write rd _r/w rd input ? read ale_as ale input ? address latch enable cs cs input active-low chip select int int output active- high interrupt rdy_dtack rdy output active-low ready ad[7:0] ad[7:0] i/o ? address/data bus
agere systems inc. 49 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) microprocessor interface register architecture the register bank architecture of the microprocessor interface is shown in table 22. addresses referred to in this section are given in decimal, with the hexadecimal representation in parentheses. table 22. device-level register map * shaded blocks are reserved for future or internal use. addr d (hex) bit number? device (ansi)* 7 (1) 6 (2) 5 (3) 4 (4) 3 (5) 2 (6) 1 (7) 0 (8) common fixed parameters?read only (ro) 0(00) int 1(01) devid[15:8] = 0x31 2(02) devid[7:0] = 0x55 3(03) devver[7:0] = 0x00 one-shot (0 to 1 transition) control bit parameters?read/write (r/w) 4(04) ta1a2erren tstgene8ins sfclear sfset sdclear sdset rstctl latch_cnt 5(05) ra1a2erren controller scratch byte?r/w 6(06) scratch[7:0] delta and event parameters?cor-ro 7(07) tilocfd ttoac_perre tlspare3 tlspare2 tlspare1 8(08) tlslofd3 tlslofd2 tlslofd1 tlsoofd3 tlsoofd2 tlsoofd1 9(09) tlsh4misd3 tlsh4misd2 tlsh4misd1 tlsptrmisd3 tlsptrmisd2 tlsptrmisd1 10(0a) rhspare rhssfd rhssdd rhslosd rhslofd rhsoofd rilocd 11(0b) rapsmond rk2mond rpaisd3 rpaisd2 rpaisd1 rlopd3 rlopd2 rlopd1 12(0c) rapsbablee rlrdimond rlaismond rj1mise rs1mond rf1mond rj0z0mond 13(0d) rhsnpimisd rhsh4mise rrdipd3 rrdipd2 rrdipd1 rc2mond3 rc2mond2 rc2mond1 14(0e) rz3mond3 rz3mond2 rz3mond1 rf2mond3 rf2mond2 rf2mond1 15(0f) rz5mond3 rz5mond2 rz5mond1 intn mask parameters?r/w 16(10) tilocfm ttoac_perrm tlsparm3 tlsparm2 tslsparm1 17(11) tlslofm3 tlslofm2 tlslofm1 tlsoofm3 tlsoofm2 tlsoofm1 18(12) tlsh4mism3 tlsh4mism2 tlsh4mism1 tlsptrmism3 tlsptrmism2 tlsptrmism1 19(13) rhsparm rhssfm rhssdm rhslosm rhslofm rhsoofm rilocm 20(14) rapsmonm rk2monm rpaism3 rpaism2 rpaism1 rlopm3 rlopm2 rlopm1 21(15) rapsbablem rlrdimonm rlaismonm rj1mism rs1monm rf1monm rj0z0monm 22(16) rhsnpimism rhsh4mism rrdipm3 rrdipm2 rrdipm1 rc2monm3 rc2monm2 rc2monm1 23(17) rz3monm3 rz3monm2 rz3monm1 rf2monm3 rf2monm2 rf2monm1 24(18) rz5monm3 rz5monm2 rz5monm1 state and value parameters?ro 25(19) tiloc tilof tlslof3 tlslof2 tlslof1 tlsoof3 tlsoof2 tlsoof1 26(1a) tprdiint tlrdiint tlsh4mis3 tlsh4mis2 tlsh4mis1 tlsptrmis3 tlsptrmis2 tlsptrmis1 27(1b) rcdrloc rhssf rhssd rhslosexti rhslos rhslof rhsoof riloc 28(1c) concat_state2[1:0] rpais3 rpais2 rpais1 rlop3 rlop2 rlop1 29(1d) rhsnpimis rlrdimon rlaismon concat_state3[1:0] rlrdiint3 rlrdiint2 rlrdiint1 receive monitor values?ro 30(1e) rj0mon[7:0] 31(1f) rz02mon[7:0] 32(20) rz03mon[7:0] 33(21) rf1mon0[7:0] 34(22) rf1mon1[7:0] 35(23) rapsmon[12:8] rk2mon[2:0] 36(24) rapsmon[7:0] 37(25) rs1mon[7:0] 38(26) rc2mon1[7:0] 39(27) rc2mon2[7:0] 40(28) rc2mon3[7:0] 41(29) rf2mon1[7:0] 42(2a) rf2mon2[7:0]
50 50 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) microprocessor interface register architecture (continued) table 22. device-level register map (continued) * shaded blocks are reserved for future or internal use. addr d (hex) bit number? device (ansi)* 7 (1) 6 (2) 5 (3) 4 (4) 3 (5) 2 (6) 1 (7) 0 (8) 43(2b) rf2mon3[7:0] 44(2c) rz3mon1[7:0] 45(2d) rz3mon2[7:0] 46(2e) rz3mon3[7:0] 47(2f) rz5mon1[7:0] 48(30) rz5mon2[7:0] 49(31) rz5mon3[7:0] 50(32) rrdip2[2:0] rrdip1[2:0] 51(33) rrdip3[2:0] mode control ? r/w 52(34) rsonet_sdh rsts3_au4 mode [1:0] ? ro febebitblockcnt bitblockcnt tsonet_sdh tsts3_au4 low-speed transmit common control signals ? r/w 53(35) tlsclkinv tlsv1disable tlsvoepar transmit low-speed port 1 input ? r/w 54(36) tsel1[2:0] tlsdscr1 55(37) tls_unequip1 tls_laisins1 tlsptrmis_aisinh1 tlsh4mis_aisinh1 tlslof_aisinh1 tlsoof_aisinh1 transmit low-speed port 2 input ? r/w 56(38) tsel2[2:0] tlsdscr2 57(39) tls_unequip2 tls_laisins2 tlsptrmis_aisinh2 tlsh4mis_aisinh2 tlslof_aisinh2 tlsoof_aisinh2 transmit low-speed port 3 input ? r/w 58(3a) tsel3[2:0] tlsdscr3 59(3b) tls_unequip3 tls_laisins3 tlsptrmis_aisinh3 tlsh4mis_aisinh3 tlslof_aisinh3 tlsoof_aisinh3 transmit high-speed clock/port control ? r/w 60(3c) thsclksel_dors thsparoeg thssa1orend thsclkinv thsptype[1:0] thsclktype[1:0] 61(3d) thsscr rhs2thslb thschiz thsshiz thsdhiz transmit high-speed control signals ? r/w 62(3e) tss[1:0] tpfebeinh tsfebeinh tj1ins ts1ins tf1ins 63(3f) tj0dins[7:0] 64(40) tz02dins[7:0] 65(41) tz03dins[7:0] 66(42) tf1dins[7:0] 67(43) tapsins[12:8] tk2ins[2:0] 68(44) tapsins[7:0] 69(45) ts1dins[7:0] 70(46) tc2dins[7:0] 71(47) tf2dins[7:0] 72(48) tz3dins[7:0] 73(49) tz5dins[7:0] transmit high-speed line rdi insertion inhibit bits ? r/w 74(4a) tlrdiinh trhssf_lrdiinh trlaismon_lrdiinh trhslof_lrdiinh trhsoof_lrdiinh trhslos_lrdiinh triloc_lrdiinh transmit high-speed path rdi insertion inhibit bits ? r/w 75(4b) tprdiins trlop1_prdiinh trpais1_prdiinh trlaismon_prdiinh trhslof_prdiinh trhsoof_prdiinh trhslos_prdiinh triloc_prdiinh transmit high-speed error insert control parameters ? r/w 76(4c) thsb3errins thsb2errins[3?1] thsb1errins 77(4d) tpfebeeins tsfebeeins tapsbableins ta1a2errins[4:0] 78(4e) th1h2crupen[3?1] th1h2crupporndf tpat23or15 tstgen_psel[1:0] receive/transmit toac control ? r/w 79(4f) rtoac_clkinv rtoacs_a1orend rtoac_oepins rtoacinh ttoac_clkinv ttoacsa1orend ttoac_oepmon ttoacinh 80(50) ttoac_e2[1:0] ttoac_e1[1:0] ttoac_d4to12[1:0] ttoac_d1to3[1:0] 81(51) ttoac_ins[1:0] ttoac_z2[1:0] ttoac_z1[1:0] ttoac_f1[1:0] transmit high-speed output offset control ? r/w 82(52) ? tstphase updwn chold cnten bypass cdr_tstshftld cdr_tstmode 83(53) tlbitcnt[2:0] tlsts1cnt[1:0] tlcolcnt[6:4] 84(54) tlcolcnt[3:0] tlrowcnt[3:0]
agere systems inc. 51 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) microprocessor interface register architecture (continued) table 22. device-level register map (continued) * shaded blocks are reserved for future or internal use. addr d (hex) bit number? device (ansi)* 7 (1) 6 (2) 5 (3) 4 (4) 3 (5) 2 (6) 1 (7) 0 (8) receive high/low-speed port control ? r/w 85(55) ths2rhslb rhsdscr rconcatmode rrdi_mpyorefc rhsvoepar rhsedge rhsptype[1:0] 86(56) j1pselmon[1:0] rsel3[1:0] rsel2[1:0] rsel1[1:0] 87(57) rlsscr[3?1] rhsporcdrsel paislop_aisinh tls2rlslb rlsclkinv rlsparoeg 88(58) rrlaismon_aisinh rrhslos_aisinh rrhslof_aisinh rrhsoof_aisinh rriloc_aisinh losdetcnt[10:8] 89(59) losdetcnt[7:0] continuous n times detect values ? r/w 90(5a) cntdf1[3:0] cntdj0z0[3:0] 91(5b) cntdaps[3:0] cntdk2[3:0] 92(5c) cntdapsframe[3:0] cntds1[3:0] 93(5d) cntdg1[3:0] cntdc2[3:0] 94(5e) cntdf2[3:0] cntdz3[3:0] 95(5f) cntdb1sel rlocinh cntcip_ici[1:0] cntdz5[3:0] receive test pattern drop ? r/w, ro 96(60) rtstdrp_oos rpat23or15 rtstdrp_psel[1:0] 97(61) rtstdrp_ecnt[7:0] receive low-speed output overhead control ? r/w 98(62) ra1a2errpen[3?1] ra1a2errins[4:0] 99(63) rb2errins[3?1] rb1errins[3?1] 100(64) rh1h2crupporndf rh1h2crupen[3?1] rf1ins[3?1] 101(65) rsfebeerrins[3?1] rsfebeinh[3?1] 102(66) rlaisins[3?1] rapsbableins[3?1] 103(67) rtiloc_lrdiinh rtlslof_lrdiinh[3?1] rtlsoof_lrdiinh[3?1] 104(68) rc1dins1[7:0] 105(69) rc1dins2[7:0] 106(6a) rc1dins3[7:0] 107(6b) rf1dins1[7:0] 108(6c) rf1dins2[7:0] 109(6d) rf1dins3[7:0] 110(6e) rapsins1[12:8] rk2dins1[2:0] 111(6f) rapsins1[7:0] 112(70) rapsins2[12:8] rk2dins2[2:0] 113(71) rapsins2[7:0] 114(72) rapsins3[12:8] rk2dins3[2:0] 115(73) rapsins3[7:0] 116(74) r_ovh_pass r_z2_pass r_f1_pass[3?1] r_e1_pass[3?1] 117(75) r_z1_pass[3?2] r_d4tod12_pass[3?1] r_d1tod3_pass[3?1] 118(76) r_e2_pass[3?1] r_s1_pass[3?1] 119(77)? 126(7e) 127(7f) page[1:0] table 23. page 0?j1 byte insert and monitor addr d (hex) bit number? device (ansi) 7 (1) 6 (2) 5 (3) 4 (4) 3 (5) 2 (6) 1 (7) 0 (8) j1 byte transmit insert ? 64 bytes ? r/w 128 (80)? 191 (bf) tj1dins[64?1][7:0] j1 byte receive monitor ? 64 bytes ? ro 192 (c0)?255 (ff) rj1mon[64?1][7:0]
52 52 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) microprocessor interface register architecture (continued) * shaded blocks are reserved for future or internal use. table 24. page 1?error counters addr d (hex) bit number? device (ansi)* 7 (1) 6 (2) 5 (3) 4 (4) 3 (5) 2 (6) 1 (7) 0 (8) transmit low-speed b1 and b2 error counts ? ro 128(80) tlsb1ecnt1[15:8] 129(81) tlsb1ecnt1[7:0] 130(82) tlsb1ecnt2[15:8] 131(83) tlsb1ecnt2[7:0] 132(84) tlsb1ecnt3[15:8] 133(85) tlsb1ecnt3[7:0] 134(86) tlsb2ecnt1[17:16] 135(87) tlsb2ecnt1[15:8] 136(88) tlsb2ecnt1[7:0] 137(89) tlsb2ecnt2[15:8] 138(8a) tlsb2ecnt2[7:0] 139(8b) tlsb2ecnt3[15:8] 140(8c) tlsb2ecnt3[7:0] receive high-speed b1, b2, and b3 error counts ? ro 141(8d) rhsb1ecnt[15:8] 142(8e) rhsb1ecnt[7:0] 143(8f) rhsb2ecnt[17:16] 144(90) rhsb2ecnt[15:8] 145(91) rhsb2ecnt[7:0] 146(92) rhsb3ecnt1[15:8] 147(93) rhsb3ecnt1[7:0] 148(94) rhsb3ecnt2[15:8] 149(95) rhsb3ecnt2[7:0] 150(96) rhsb3ecnt3[15:8] 151(97) rhsb3ecnt3[7:0] receive high-speed pointer increment and decrement counters ? ro 152(98) rptr_inc1[10:8] 153(99) rptr_inc1[7:0] 154(9a) rptr_inc2[10:8] 155(9b) rptr_inc2[7:0] 156(9c) rptr_inc3[10:8] 157(9d) rptr_inc3[7:0] 158(9e) rptr_dec1[10:8] 159(9f) rptr_dec1[7:0] 160(a0) rptr_dec2[10:8] 161(a1) rptr_dec2[7:0] 162(a2) rptr_dec3[10:8] 163(a3) rptr_dec3[7:0] receive high-speed section/path febe counts ? ro 164(a4) rsfebecnt[17:16] 165(a5) rsfebecnt[15:8] 166(a6) rsfebecnt[7:0] 167(a7) rpfebecnt1[15:8] 168(a8) rpfebecnt1[7:0] 169(a9) rpfebecnt2[15:8] 170(aa) rpfebecnt2[7:0] 171(ab) rpfebecnt3[15:8] 172(ac) rpfebecnt3[7:0]
agere systems inc. 53 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) microprocessor interface register architecture (continued) * shaded blocks are reserved for future or internal use. table 25. page 2?ber algorithm parameters addr d (hex) bit number? device (ansi)* 7 (1) 6 (2) 5 (3) 4 (4) 3 (5) 2 (6) 1 (7) 0 (8) signal degrade set/clear control registers ? r/w 128(80) sdnsset[18:16] 129(81) sdnsset[15:8] 130(82) sdnsset[7:0] 131(83) sdb1b2sel sdlset[3:0] 132(84) sdmset[7:0] 133(85) sdbset[15:8] 134(86) sdbset[7:0] 135(87) sdnsclear[18:16] 136(88) sdnsclear[15:8] 137(89) sdnsclear[7:0] 138(8a) sdlclear[3:0] 139(8b) sdmclear[7:0] 140(8c) sdbclear[15:8] 141(8d) sdbclear[7:0] signal fail set/clear control registers ? r/w 142(8e) sfnsset[18:16] 143(8f) sfnsset[15:8] 144(90) sfnsset[7:0] 145(91) sfb1b2sel sflset[3:0] 146(92) sfmset[7:0] 147(93) sfbset[15:8] 148(94) sfbset[7:0] 149(95) sfnsclear[18:16] 150(96) sfnsclear[15:8] 151(97) sfnsclear[7:0] 152(98) sflclear[3:0] 153(99) sfmclear[7:0] 154(9a) sfbclear[15:8] 155(9b) sfbclear[7:0] 156(9c)? 255(ff) invalid
54 54 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) register description this section gives a brief description of each register bit and its functionality. all algorithms are described in the main text of the document or in the maintenance section of the document. the abbreviations after each register indicate if the register is read only (ro), clear-on-read (cor), or read/write (r/w). table 26. register 0 (ro) table 27. registers 1?3 (ro) table 28. registers 4, 5: one-shot register 0 1 (r/w) address dec (hex) bit name function reset default 0 (0x00) 0 int interrupt. the active-high bit is a copy of the int pin. this bit is the oring of all event and delta bits (registers 0x07?0x0f). an event or delta bit contribution can be inhibited from contributing to this bit by setting the appropriate mask bit (see mask bit operation on page 28). 0 address dec (hex) bit name function reset default 1 (0x01) 7?0 devid[15:8] device id. upper device id byte of the number which uniquely identifies the device. 0x31 2 (0x02) 7?0 devid[7:0] device id. lower device id byte of the number which uniquely identifies the device. 0x55 3 (0x03) 7?0 devver[7:0] device version number. device version register will change each time the device is changed. 0x03 address dec (hex) bit name function reset default 4 (0x04) 7 ta1a2erren transmit a1/a2 error enable. inserts framing errors into the output sts-3/stm-1 (au-4) signal. the number of consecutive errors is controlled by ta1a2errins[4:0], 0x4d. 0 4 (0x04) 6 tstgene8ins test generation 8 error insert. inserts eight errors into the pseudorandom signal being inserted into the selected tug-3 signal. 0 4 (0x04) 5 sfclear signal fail clear. allows the signal fail algorithm to be forced into the normal state. 0 4 (0x04) 4 sfset signal fail set. allows the signal fail algorithm to be forced into the failed state. 0 4 (0x04) 3 sdclear signal degrade clear. allows the signal degrade algorithm to be forced into the normal state. 0 4 (0x04) 2 sdset signal degrade set. allows the signal degrade algorithm to be forced into the failed state. 0
agere systems inc. 55 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) register description (continued) table 28. registers 4, 5: one-shot register 0 1 (r/w) (continued ) table 29. register 6: scratch register (r/w) table 30. registers 7?15: delta/event (cor-ro) address dec (hex) bit name function reset default 4 (0x04) 1 rstctl reset control (software). resets the device. this reset has the same effect as the external reset pin. this is a service affecting action. all state machines and registers bits will revert to their default values. 0 4 (0x04) 0 latch_cnt latch count. causes all counters to latch their val- ues and clear their internal counters, except the test drop counter. these counters are large enough to hold at least one second?s worth of data. 0 5 (0x05) 7 ra1a2erren receive a1/a2 error enable. inserts framing errors into the respective output sts-1/au-3 signal. 0 address dec (hex) bit name function reset default 6 (0x06) 7?0 scratch [7:0] scratch register. allows the control system to verify read and write operations to the device without affecting device operation. 0x00 address dec (hex) bit name function reset default 7 (0x07) 7 tilocfd transmit input loss of clock and frame delta. delta bit indicates a change of state for the local clock (tiloc, 0x19) or frame sync (tilof, 0x19). the delta bit clears when read. its mask bit is tilocfm, 0x10. note: the tilof state is not supported in version 3 of the device. 0 7 (0x07) 3 ttoac_perre transmit transport overhead access channel (toac) parity error event. event register indicates a parity error was detected on the incoming transmit section overhead access channel. the bit will be cleared when read, but will be set again if the condition persists. its mask bit is ttoac_perrm, 0x10. 0 7 (0x07) 2?0 tlspare[3?1] transmit low-speed parity error event (input port number). indicates a byte transfer parity error on the respective sts-1/au-3 input. these bits will clear when read, but will be set again if the condi- tion persists. their mask bits are tlsparm[3?1], 0x10. 000
56 56 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) register map (continued) table 30. registers 7?15: delta/event (cor-ro) (continued) address dec (hex) bit name function reset default 8 (0x08) 5?3 tlslofd[3?1] transmit low-speed loss-of-frame delta. delta bits indicate a change in state of the loss-of-frame (tlslof[3?1], 0x19) monitor on each sts-1/au- 3 input. the associated mask bits are tlslofm[3?1], 0x10. 000 8 (0x08) 2?0 tlsoofd[3?1] transmit low-speed out-of-frame delta. delta bits indicate a change in state of the out-of-frame (tlsoof[3?1], 0x19) monitor on each sts-1/ au-3 input. the associated mask bits are tlsoofm[3?1], 0x11. 000 9 (0x09) 5?3 tlsh4misd[3?1] transmit low-speed h4 mismatch delta. delta bits indicate a change in state of the h4 multiframe pointer mismatch (tlsh4mis[3?1], 0x1a) monitor on each au-3 input. the associated mask bits are tlsh4mism[3?1], 0x12. 000 9 (0x09) 2?0 tlsptrmisd[3?1] transmit low-speed pointer mismatch delta. delta bits indicate a change in state of the pointer value monitor (h1, h2) (tlsptrmis[3?1], 0x1a) on each au-3 input. the associated mask bits are tlsptrmism[3?1], 0x12. 000 10 (0x0a) 7 rhspare receive high-speed parity error event. event bit indicates a parity error was detected on a nibble/ byte transfer on the sts-3/stm-1 (au-4) input. its mask bit is rhsparm, 0x13. 0 10 (0x0a) 6 rhssfd receive high-speed signal fail delta . receive high-speed signal degrade delta. delta bits are set each time the signal fail and signal degrade state values change (rhssf, 0x1b, rhssd, 0x1b), respectively. the associated mask bits are rhssfm, 0x13 and rhssdm, 0x13. 0 10 (0x0a) 5 rhssdd 0 10 (0x0a) 3 rhslosd receive high-speed loss-of-signal delta. delta bit indicates a change in state (rhslos, rhslosexti, 0x1b) when a loss of signal is detected. it clears on the incoming sts-3/stm-1 (au-4) input. the rhslosexti is an external input from a device pin. rhslos is an internal indicator monitoring for a consecutive zero/ones pattern in the unscrambled data input. its mask bit is rhslosm, 0x13. 0
agere systems inc. 57 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) register map (continued) table 30. registers 7?15: delta/event (cor-ro) (continued) address dec (hex) bit name function reset default 10 (0x0a) 2 rhslofd receive high-speed loss-of-frame. delta bit indicates a change in state (rhslof), 0x1b when a loss of frame is detected. it clears on the incoming sts-3/stm-1 (au-4) input. its mask bit is rhslofm, 0x13. 0 10 (0x0a) 1 rhsoofd receive high-speed out-of-frame delta. delta bit indicates a change in state (rhsoof, 0x1b) when an out of frame is detected. it clears on the incoming sts-3/stm-1 (au-4) input. its mask bit is rhsoofm, 0x13. 0 10 (0x0a) 0 rilocd receive input loss-of-clock delta. delta bit indi- cates a change in state (riloc, 0x1b) of the receive sts-3/stm-1 (au-4) input clock. its mask bit is rilocm, 0x13. 0 11 (0x0b) 7 rapsmond receive aps (k1, k2 bytes) monitor delta. delta bit indicates a change in state (rapsmon[12:0], 0x23?24) when a new consistent value is detected (cntdaps[3:0], 0x5b) in the incoming k1 and k2[7:3] bits of the input sts-3/stm-1 (au-4) frame. its mask bit is rapsmonm, 0x14. 0 11 (0x0b) 6 rk2mond receive k2 [2:0] monitor delta. this feature is not supported in version 3 of the device. 0 11 (0x0b) 5?3 rpaisd[3?1] receive path ais delta. delta bit indicates a change in state (rpais[3?1], 0x1c) when the pointer state machines declare path ais (all ones in the h1 and h2 bytes) on the receive sts-3/stm-1 (au-4) signal. its mask bit is rpaism[3?1], 0x14. only port 1 information is valid in au-4 mode. 000 11 (0x0b) 2?0 rlopd[3?1] receive loss-of-pointer delta. delta bit indicates a change in state (rlop[3?1], 0x1c) when the pointer state machines declare loss of pointer on the receive sts-3/stm-1 (au-4) signal. its mask bit is rlopm[3?1], 0x14. only port 1 information is valid in au-4 mode. 000
58 58 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) register map (continued) table 30. registers 7?15: delta/event (cor-ro) (continued) address dec (hex) bit name function reset default 12 (0x0c) 7 rapsbablee receive aps babble event. event bit indicates when an inconsistent aps value has been detected cntdaps[3:0], 0x5b times in the incoming cntdapsframe[3:0], 0x5c frames. its mask bit is rapsbablem, 0x15 . 0 12 (0x0c) 6 rlrdimond receive line-rdi monitor delta. delta bit indi- cates a change in state (rlrdimon, 0x1d) when the pattern 110 is detected/not detected cntdk2[2:0], 0x1b consecutive times in the incoming sts-3/stm-1 (au-4) frame. its mask bit is rlrdimonm, 0x15. 0 12 (0x0c) 5 rlaismond receive line-ais monitor delta. delta bit indi- cates a change in state (rlaismon, 0x10) when the pattern 111 is detected/not detected cntdk2[2:0], 0x5b consecutive times in the incoming sts-3/stm-1 (au-4) frame. its mask bit is rlaismonm, 0x15. 0 12 (0x0c) 3 rj1mise receive j1 mismatch event. event bit indicates a change in state in the received j1 64-byte sequence (rj1mon[64?1][7:0], 0xc0?0xff). its mask bit is rj1mism, 0x15. 0 12 (0x0c) 2 rs1mond receive s1 (sync status) byte monitor delta. delta bit indicates a change in state (rs1mon[7:0], 0x25) when a consecutive and consistent new value (cntds1[3:0], 0x5c) is detected in the incoming s1 byte of the sts-3/stm-1 (au-4) frame. its mask bit is rs1monm, 0x15. 0 12 (0x0c) 1 rf1mond receive f1 byte monitor delta. delta bit indicates a change in state (rf1mon1[7:0], 0x22, rf1mon0[7:0], 0x21) when a consecutive and consistent new value (cntdf1[3:0], 0x5a) is detected in the incoming f1 byte of the sts-3/ stm-1 (au-4) frame. state byte rf1mon0[7:0] is the current new value, rf1mon1[7:0] is the previ- ous f1 value. its mask bit is rf1monm, 0x15. 0
agere systems inc. 59 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) register map (continued) table 30. registers 7?15: delta/event (cor-ro) (continued) address dec (hex) bit name function reset default 12 (0x0c) 0 rj0z0mond receive composite j0, z0-2, z0-3 monitor delta. delta bit indicates a change in state (rj0mon[7:0], 0x1e, rz02mon[7:0], 0x1f, rz03mon[7:0], 0x20) when a consecutive and consistent new value (cntdj0z0[3:0], 0x5a) is detected in the incoming j0, z0-2, z0-3, bytes of the sts-3/stm-1 (au-4) frame. its mask bit is rj0z0monm, 0x15. 0 13 (0x0d) 7 rhsnpimisd receive high-speed null pointer indicator (npi) delta. delta bit indicates a change in state (rhsnpimis, 0x1d): a mismatch is declared when five consecutive mismatches occur separated in time by 125 s in the received npi value, a match is declared when two consecutive valid npi values (byte 1 = 10011011, byte 2 = 11100000) are received spaced 125 s apart in the stm-1 (au-4) frame. its mask bit is rhsnpimism, 0x16. 0 13 (0x0d) 6 rhsh4mise receive high-speed h4 mismatch event. event bit indicates when the received h4 value does not agree with the expected value. the sequence 00, 01, 10, and 11 should repeat in consecutive frames. when a mismatch occurs, the device will accept that new value + 1 as the expected value for the next frame. its mask bit is rhsh4mism, 0x16 . 0 13 (0x0d) 5?3 rrdipd[3?1] receive rdi-p (g1 byte) delta. delta bit indicates a change in state (rrdip[3?1][2:0], 0x32?0x33) when a consecutive and consistent new value (cntdg1[3:0], 0x5d) is detected in the incoming g1[3:1] bits of the sts-3/stm-1 (au-4) frame. its mask bit is rrdipm[3?1], 0x16. the device will either monitor g1 bit 3 as a path yellow (rrdi_mpyorefc = 0) or g1 bits 3 down to 1 as an enhanced failure code (rrdi_mpyorefc = 1) under software control. only port 1 information is valid in au-4 mode. 000
60 60 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) register map (continued) table 30. registers 7?15: delta/event (cor-ro) (continued) table 31. registers 16?24: mask bits (r/w) address dec (hex) bit name function reset default 13 (0x0d) 2?0 rc2mond[3?1] receive c2 (signal label) monitor delta. delta bit indicates a change in state (rc2mon [3?1][7:0], 0x26?28) when a consecutive and consistent new value (cntdc2[3:0], 0x5d) is detected in the incoming c2 bytes of the sts-3/ stm-1 (au-4) frame. its mask bit is rc2monm[3?1], 0x16. only port 1 information is valid in au-4 mode. 000 14 (0x0e) 5?3 rz3mond[3?1] receive z3 (growth) monitor delta. delta bit indi- cates a change in state (rz3mon[3?1][7:0], 0x2c?2e) when a consecutive and consistent new value (cntdz3[3:0], 0x5e) is detected in the incoming z3 bytes of the sts-3/stm-1 (au-4) frame. its mask bit is rz3monm[3?1], 0x17. only port 1 information is valid in au-4 mode. 000 14 (0x0e) 2?0 rf2mond[3?1] receive f2 (user channel) monitor delta. delta bit indicates a change in state (rf2mon[3?1][7:0], 0x29?2b) when a consecutive and consistent new value (cntdf2[3:0], 0x5e) is detected in the incoming f2 bytes of the sts-3/stm-1 (au-4) frame. its mask bit is rf2monm[3?1], 0x17. only port 1 information is valid in au-4 mode. 000 15 (0x0f) 2?0 rz5mond[3?1] receive z5 (tandem connection) monitor delta. delta bit indicates a change in state (rz5mon [3?1][7:0], 0x31) when a consecutive and consis- tent new value (cntdz5[3:0], 0x5f) is detected in the incoming z5 bytes of the sts-3/stm-1 (au-4) frame. its mask bit is rz5monm[3?1], 0x18. only port 1 information is valid in au-4 mode. 000 address dec (hex) bit name function reset default 16 (0x10) 7 tilocfm transmit input loss-of-clock and frame mask. see (addr 0x07) for description. 0 16 (0x10) 3 ttoac_perrm transmit toac parity error mask. see (addr 0x07) for description. 0 16 (0x10) 2?0 tlsparm[3?1] transmit low-speed parity error mask. see (addr 0x07) for description. 000
agere systems inc. 61 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) register map (continued) table 31. registers 16?24: mask bits (r/w) (continued) address dec (hex) bit name function reset default 17 (0x11) 5?3 tlslofm[3?1] transmit low-speed loss-of-frame mask. see (addr 0x08) for description. 000 17 (0x11) 2?0 tlsoofm[3?1] transmit low-speed out-of-frame mask. see (addr 0x08) for description. 000 18 (0x12) 5?3 tlsh4mism[3?1] transmit low-speed h4 mismatch mask. see (addr 0x09) for description. 000 18 (0x12) 2?0 tlsptrmism[3?1] transmit low-speed pointer mismatch mask. see (addr 0x09) for description. 000 19 (0x13) 7 rhsparm receive high-speed parity error mask. see (addr 0x0a) for description. 0 19 (0x13) 6 rhssfm receive high-speed signal fail mask. see (addr 0x0a) for description. 0 19 (0x13) 5 rhssdm receive high-speed signal degrade mask. see (addr 0x0a) for description. 0 19 (0x13) 3 rhslosm receive high-speed loss-of-signal mask. see (addr 0x0a) for description. 0 19 (0x13) 2 rhslofm receive high-speed loss-of-frame mask. see (addr 0x0a) for description. 0 19 (0x13) 1 rhsoofm receive high-speed out-of-frame mask. see (addr 0x0a) for description. 0 19 (0x13) 0 rilocm receive input loss-of-clock mask. see (addr 0x0a) for description. 0 20 (0x14) 7 rapsmonm receive aps monitor mask. see (addr 0x0b) for description. 0 20 (0x14) 6 rk2monm receive k2 monitor mask. see (addr 0x0b) for description. 0 20 (0x14) 5?3 rpaism[3?1] receive path ais mask. see (addr 0x0b) for description. 000 20 (0x14) 2?0 rlopm[3?1] receive loss-of-pointer mask. see (addr 0x0b) for description. 000 21 (0x15) 7 rapsbablem receive aps babble mask. see (addr 0x0c) for description. 0 21 (0x15) 6 rlrdimonm receive line rdi monitor mask. see (addr 0x0c) for description. 0 21 (0x15) 5 rlaismonm receive line ais monitor mask. see (addr 0x0c) for description. 0 21 (0x15) 2 rs1monm receive s1 monitor mask. see (addr 0x0c) for description. 0 21 (0x15) 3 rj1mism receive j1 mismatch mask. see (addr 0x0c) for description. 0 21 (0x15) 1 rf1monm receive f1 monitor mask. see (addr 0x0c) for description. 0 21 (0x15) 0 rj0z0monm receive j0, z0-2, z0-3 monitor mask. see (addr 0x0c) for description. 0
62 62 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) register map (continued) table 31. registers 16?24: mask bits (r/w) (continued) table 32. registers 25?51: state bits (ro) address dec (hex) bit name function reset default 22 (0x16) 7 rhsnpimism receive high-speed npi mismatch mask. see (addr 0x0d) for description. 0 22 (0x16) 6 rhsh4mism receive high-speed h4 mismatch mask. see (addr 0x0d) for description. 0 22 (0x16) 5?3 rrdipm[3?1] receive rdi-p mask. see (addr 0x0d) for descrip- tion. 000 22 (0x16) 2?0 rc2monm[3?1] receive c2 monitor mask. see (addr 0x0d) for description. 000 23 (0x17) 5?3 rz3monm[3?1] receive z3 monitor mask. see (addr 0x0e) for description. 000 23 (0x17) 2?0 rf2monm[3?1] receive f2 monitor mask. see (addr 0x0e) for description. 000 24 (0x18) 2?0 rz5monm[3?1] receive z5 monitor mask. see (addr 0x0f) for description. 000 address dec (hex) bit name function reset default 25 (0x19) 7 tiloc transmit input loss-of-clock (state). see (addr 0x07) for description. unde- fined. 25 (0x19) 6 tilof transmit input loss-of-frame (state). see (addr 0x07) for description. note: this feature is not supported in version 3 of the device. unde- fined. 25 (0x19) 5?3 tlslof[3?1] transmit low-speed loss-of-frame (state). see (addr 0x08) for description. 111 25 (0x19) 2?0 tlsloof[3?1] transmit low-speed out-of-frame (state). see (addr 0x08) for description. 111 26 (0x1a) 7 tprdiint transmit rdi-p internal (state). state bit indicates when path rdi is active. (valid only in au-4 mode.) 1 26 (0x1a) 6 tlrdiint transmit rdi-l internal (state). state bit indicates when line rdi is active. 1 26 (0x1a) 5?3 tlsh4mis[3?1] transmit low-speed h4 mismatch (state). see (addr 0x09) for description. 000 26 (0x1a) 2?0 tlsptrmis[3?1] transmit low-speed pointer mismatch (state). see (addr 0x09) for description. 000 27 (0x1b) 7 rcdrloc receive clock data recovery loss-of-clock (state). state bit indicates when the internal cdr clock is missing. this is an active-high signal. unde- fined. 27 (0x1b) 6 rhssf receive high-speed signal fail (state). see (addr 0x0a) for description. 1 27 (0x1b) 5 rhssd receive high-speed signal degrade (state). see (addr 0x0a) for description. 1
agere systems inc. 63 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) register map (continued) table 32. registers 25?51: state bits (ro) (continued) address dec (hex) bit name function reset default 27 (0x1b) 4 rhslosexti receive high-speed loss-of-signal (external). see (addr 0x0a) for description. input pin value. 27 (0x1b) 3 rhslos receive high-speed loss-of-signal (state). see (addr 0x0a) for description. 1 27 (0x1b) 2 rhslof receive high-speed loss-of-frame (state). see (addr 0x0a) for description. 1 27 (0x1b) 1 rhsoof receive high-speed out-of-frame (state). see (addr 0x0a) for description. 1 27 (0x1b) 0 riloc receive input loss-of-clock (state). see (addr 0x0a) for description. unde- fined. 28 (0x1c) 5?3 rpais[3?1] receive path ais (state). see (addr 0x0b) for description. 111 28 (0x1c) 2?0 rlop[3?1] receive loss-of-pointer (state). see (addr 0x0b) for description. 111 29 (0x1d) 7 rhsnpimis receive high-speed npi mismatch (state). see (addr 0x0d) for description. 1 29 (0x1d) 6 rlrdimon receive rdi-l monitor (state). see (addr 0x0c) for description. 0 28 (0x1c) 29 (0x1d) 7?6 4?3 concat_state [2?3][1:0] concatenation pointer state machine state. state bits indicate the state of the concatenation state machine (lopc = 10, aisc = 01, conc = 00). these values only have meaning in the au-4 mode and the rconcatmode bit (addr 0x55) set to the concatenation mode (1). 10 29 (0x1d) 5 rlaismon receive ais-l monitor (state). state bit indicates a consistent consecutive k2[2:0] value of 111 has been detected (cntdk1[3:0]) times. 0 29 (0x1d) 2?0 rlrdiint[3?1] receive rdi-l internal (state). state bits indicate when line rdi conditions are active on a per sts- 1/au-3 basis in the device receive path. 111 30 (0x1e) 7?0 rj0mon[7:0] receive j0 monitor value. see (addr 0x0c) for description. 0x00 31 (0x1f) 7?0 rz02mon[7:0] receive z0-2 monitor value. see (addr 0x0c) for description. 0x00 32 (0x20) 7?0 rz03mon[7:0] receive z0-3 monitor value. see (addr 0x0c) for description. 0x00 33 (0x21) 7?0 rf1mon0[7:0] receive f1 current monitor value. see (addr 0x0c) for description. 0x00 34 (0x22) 7?0 rf1mon1[7:0] receive f1 previous monitor value. see (addr 0x0c) for description. 0x00 35 (0x23) 2?0 rk2mon[2:0] receive k2 monitor value. see (addr 0x0b) for description. 000
64 64 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) register map (continued) table 32. registers 25?51: state bits (ro) (continued) table 33. register 52: mode control (r/w) address dec (hex) bit name function reset default 35 (0x23) 36 (0x24) 7?3 7?0 rapsmon[12:8] rapsmon[7:0] receive aps monitor value. see (addr 0x0b) for description. 0000000 000000 37 (0x25) 7?0 rs1mon[7:0] receive s1 monitor value. see (addr 0x0c) for description. 0x00 38 (0x26) 39 (0x27) 40 (0x28) 7?0 rc2mon[1?3][7:0] receive c2 monitor path values. see (addr 0x0d) for description. 0x00 41 (0x29) 42 (0x2a) 43 (0x2b) 7?0 rf2mon[1?3][7:0] receive f2 monitor path values. see (addr 0x0e) for description. 0x00 44 (0x2c) 45 (0x2d) 46 (0x2e) 7?0 rz3mon[1?3][7:0] receive z3 monitor path values. see (addr 0x0e) for description. 0x00 47 (0x2f) 48 (0x30) 49 (0x31) 7?0 rz5mon[1?3][7:0] receive z5 monitor path values. see (addr 0x0f) for description. 0x00 50 (0x32) 50 (0x32) 51 (0x33) 5?3 2?0 2?0 rrdip2[2:0] rrdip1[2:0] rrdip3[2:0] receive rdi-p monitor path values (g1 byte). see (addr 0x0d) for description. 000 address dec (hex) bit name function reset default 52 (0x34) 7 rsonet_sdh receive sonet or sdh mode. control bit, when set to a logic 0, puts the device receive path into the sonet mode ; otherwise, the device receive path remains in sdh mode. for sts-1 mode, set both rsonet_sdh and rsts3_au4 to a logic 0, and tie the external mode control pins low. 0 52 (0x34) 6 rsts3_au4 receive sts3 or au4 mode. control bit, when set to a logic 0, puts the device receive path into the sts-3 mode (three sts-1 signals multiplexed into an sts-3 signal); otherwise, au-4 mode (three au- 3 signals multiplexed into an stm-1 (au-4) signal). for sts-1 mode, set both rsonet_sdh and rsts3_au4 to a logic 0, and tie the external mode control pins low. 0 52 (0x34) 5?4 mode [1:0] mode value from external pins (ro). read-only status bits allow monitoring of the external mode control pins. must be set to 10.
agere systems inc. 65 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) register map (continued) table 33. register 52: mode control (r/w) (continued) table 34. register 53: low-speed transmit common signals (r/w) address dec (hex) bit name function reset default 52 (0x34) 3 febebitblockcnt far-end block error (febe) bit or block count (control). control bit, when set to a logic 0, causes the febe counters to count bit errors; otherwise, count block errors (a block equals one frame). 0 52 (0x34) 2 bitblockcnt bit or block error count (control) . control bit, when set to a logic 0, causes the counters to count bit errors; otherwise, count block errors (a block equals one frame). 0 52 (0x34) 1 tsonet_sdh transmit sonet or sdh. control bit, when set to a logic 0, puts the device transmit path into the sonet mode; otherwise, sdh mode. 0 52 (0x34) 0 tsts3_au4 transmit sts3 or au4 mode. control bit, when set to a logic 0, puts the device transmit path into the sts-3 mode (sts-3 signal demultiplexed into three sts-1 signals); otherwise, au-4 mode (stm-1 (au-4) signal demultiplexed into three au-3 signals). 0 address dec (hex) bit name function reset default 53 (0x35) 2 tlsclkinv transmit low-speed clock invert control. con- trol bit, when set to a logic 1, causes the output clock to be inverted; otherwise, do not invert the output clock before leaving the device. 0 53 (0x35) 1 tlsv1disable transmit low-speed v1 disable control . control bit, when set to a logic 1, disables the generation of v1 time signal on the transmit low-speed bus inter- face. 0 53 (0x35) 0 tlsvoepar transmit low-speed verify odd or even parity. control bit, when set to a logic 0, causes odd parity to be verified per byte transfer per sts-1/au-3 input; otherwise, even parity is verified. 0
66 66 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) register map (continued) table 35. register 54?59: transmit low-speed port input control (r/w) address dec (hex) bit name function reset default 54 (0x36) 56 (0x38) 58 (0x3a) 7?5 tsel[1?3][2:0] transmit select control. control bits allow input selection and loopback operation to occur on a per sts-1/au-3 input basis (see table 5, input select control, on page 17). 010 001 000 54 (0x36) 56 (0x38) 58 (0x3a) 0 tlsdscr[1?3] transmit low-speed descramble control. con- trol bit, when set to a logic 1, causes the selected sts-1/au-3 input signal to be descrambled. 0 55 (0x37) 57 (0x39) 59 (0x3b) 7 tls_unequip[1?3] transmit low-speed unequipped insert con- trol. control bit, when set to a logic 1, causes an unequip signal to be generated in the selected sts-1/au-3 time slot in the sts-3/stm-1 (au-4) output signal; normal data is sent when set to a logic 0. only tls_unequip1 is used in au-4 mode. 0 55 (0x37) 57 (0x39) 59 (0x3b) 6 tls_laisins[1?3] transmit low-speed line ais insert control. control bit, when set to a logic 1, causes an ais signal to be inserted into the selected sts-1/tug-3 time slot in the sts-3/stm-1 (au-4) output signal; normal data is sent when set to a logic 0. only tls_laisins1 is used in au-4 mode. 0 55 (0x37) 57 (0x39) 59 (0x3b) 3 tlsptrmis_aisinh [1?3] transmit low-speed pointer mismatch ais inhibit control. control bit, when set to a logic 1, causes the associated failure not to contribute to the automatic insertion of ais-l in the associated output time slot; otherwise, allow the associated alarm to contribute to the generation of ais-l. 1 55 (0x37) 57 (0x39) 59 (0x3b) 2 tlsh4mis_aisinh [1?3] transmit low-speed h4 mismatch ais inhibit control. same as above. 1 55 (0x37) 57 (0x39) 59 (0x3b) 1 tlslof_aisinh[1?3] transmit low-speed loss-of-frame ais inhibit control. same as above. 1 55 (0x37) 57 (0x39) 59 (0x3b) 0 tlsoof_aisinh[1?3] transmit low-speed out-of-frame ais inhibit control. same as above. 0
agere systems inc. 67 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) register map (continued) table 36. registers 60, 61: transmit high-speed clock/port control (r/w) address dec (hex) bit name function reset default 60 (0x3c) 7 thsclksel_dors transmit high-speed clock select differential or single-ended inputs. control bit, when set to a logic 0, selects the differential clock and sync inputs (thssclkit/c (pins 143, 142), thssj0j1v1it/c (pins 140, 139)) for driving the transmit direction of the device; otherwise, the single-ended inputs (thsclki, thsj0j1v1i) are selected. 0 60 (0x3c) 6 thsparoeg transmit high-speed parity odd or even gener- ation. control bit, when set to a logic 0, causes odd parity to be inserted in nibble/parallel mode per clock transfer on the sts-3/stm-1 (au-4) output; a logic 1 causes even parity to be generated. 0 60 (0x3c) 5 thssa1orend transmit high-speed a1 or end sync align- ment. control bit, when set to a logic 0, causes the output sync to be coincident with the first bit, nibble, or byte of the outgoing frame; a logic 1 causes the sync to be coincident with the last bit, nibble, or byte of the frame. 0 60 (0x3c) 4 thsclkinv transmit high-speed clock invert. control bit, when set to a logic 1, causes the output clock to be inverted, a logic 0 doesn?t effect the clock. 0 60 (0x3c) 3?2 thsptype[1:0] transmit high-speed port type. control bits con- trol the type of output port (sts-3/stm-1 (au-4): 00 = serial, 01 = nibble, 10 = byte mode). 00 60 (0x3c) 1?0 thsclktype[1:0] transmit high-speed clock type. control bits control the type of transmit clock being provided to the device: 00 = serial clock (155.52 mhz), 01 = nibble clock (38.88 mhz), 10 = byte clock (19.44 mhz). 00
68 68 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) register map (continued) table 36. registers 60, 61: transmit high-speed clock/port control (r/w) (continued) table 37. register 62: transmit high-speed control signals (r/w) address dec (hex) bit name function reset default 61 (0x3d) 7 thsscr transmit high-speed scramble enable. control bit, when set to a logic 1, causes the output sts-3/ stm-1 (au-4) signal to be scrambled; the signal is not scrambled if set to a logic 0. 0 61 (0x3d) 6 rhs2thslb receive high-speed to transmit high-speed loopback control. control bit, when set to a logic 1, causes the receive sts-3/stm-1 (au-4) input signal to be looped back to the transmit high-speed output; loopback is disabled when set to a logic 0. 0 61 (0x3d) 2 thschiz transmit high-speed clock high-impedance (control). control signal, when set to a logic 1, causes the output sts-3/stm-1 (au-4) clock to be placed in a high-impedance state; a logic 0 enables the output driver. 0 61 (0x3d) 1 thsshiz transmit high-speed sync high-impedance (control). control signal, when set to a logic 1, causes the output sts-3/stm-1 (au-4) sync signal to be placed in a high-impedance state; a logic 0 enables the output driver. 0 61 (0x3d) 0 thsdhiz transmit high-speed data high-impedance (control). control signal, when set to a logic 1, causes the output sts-3/stm-1 (au-4) data sig- nals to be placed in a high-impedance state; a logic 0 enables the output drivers. 0 address dec (hex) bit name function reset default 62 (0x3e) 7?6 tss[1:0] transmit ss (bits). these bits are used in the sts-1 mode to set the ss bits when an unequipped signal is being generated. 00 62 (0x3e) 4 tpfebeinh transmit path febe inhibit. control bit, when set to a logic 1, disables hardware insertion of path febe (b3 errors) in the outgoing stm-1 (au-4) frame g1 byte; a logic 0 enables hardware insertion of pfebe. only valid in au-4 mode. 0 62 (0x3e) 3 tsfebeinh transmit section febe inhibit. control bit, when set to a logic 1, disables hardware insertion of sec- tion febe (b2 errors) in the outgoing sts-3/stm-1 frame m1 byte; a logic 0 enables hardware insertion of sfebe. 0
agere systems inc. 69 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) register map (continued) table 38. register 62, and page 0, registers 128?191: transmit high-speed j1 insert (r/w) table 39. register 62, 69: transmit high-speed control signals (r/w) table 40. register 62, 66: transmit high-speed control signals (r/w) table 41. registers 63?65: trace/growth bytes (r/w) address dec (hex) bit name function reset default 62 (0x3e) 2 tj1ins transmit j1 insert (control). control bit, when set to a logic 1, inserts the 64-byte sequence tj1dins[64 ?1][7:0], page 0, 0x80?bf into the outgoing sts-3/stm-1 (au-4) frame; a logic 0 inserts an all-zeros pattern (0x00 for all 64 bytes of the j1dins bytes). the tj1dins[64?1][7:0] val- ues are unchanged. 0 address dec (hex) bit name function reset default 62 (0x3e) 1 ts1ins transmit s1 insert (control). control bit, when set to a logic 1, inserts the value in ts1dins[7:0], 0x45 into the outgoing s1 byte in the sts-3/stm-1 (au-4) frame; a logic 0 inserts the default value. 0 address dec (hex) bit name function reset default 62 (0x3e) 0 tf1ins transmit f1 insert (control). control bit, when set to a logic 1, inserts the value in tf1dins[7:0], 0x42 into the outgoing f1 byte in the sts-3/stm-1 (au-4) frame; a logic 0 inserts the default value. 0 address dec (hex) bit name function reset default 63 (0x3f) 7?0 tj0dins[7:0] transmit j0 data insert value. register value is inserted into the sts-3/stm-1 (au-4) output j0 byte. 0x01 64 (0x40) 7?0 tz02dins[7:0] transmit z0-2 data insert value. register value is inserted into the sts-3/stm-1 (au-4) output z0-2 byte. 0x02 65 (0x41) 7?0 tz03dins[7:0] transmit z0-3 data insert value. register value is inserted into the sts-3/stm-1 (au-4) output z0-3 byte. 0x03
70 70 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) register map (continued) table 42. register 66: transmit f1 data byte (r/w) table 43. registers 67 and 68: k1 and k2 insert bytes (r/w) table 44. register 69: transmit sync status byte (r/w) table 45. register 70: path signal trace byte (r/w) table 46. register 71: path user channel byte (r/w) table 47. register 72: path growth byte (r/w) address dec (hex) bit name function reset default 66 (0x42) 7?0 tf1dins[7:0] transmit f1 data insert value. see (addr 0x3e) for description. 0x00 address dec (hex) bit name function reset default 67 (0x43) 68 (0x44) 7?3 7?0 tapsins[12:8] tapsins[7:0] transmit aps data insert value. register value is inserted into the sts-3/stm-1 (au-4) output k1[7:0] and k2[7:3] bits. 0000000 000000 67 (0x43) 2?0 tk2ins[2:0] transmit k2 data insert value. register value is inserted into the sts-3/stm-1 (au-4) output k2[2:0] bits. 000 address dec (hex) bit name function reset default 79 (0x45) 7?0 ts1dins [7:0] transmit s1 data insert value. see (addr 0x3e) for description. 0x00 address dec (hex) bit name function reset default 70 (0x46) 7?0 tc2dins [7:0] transmit c2 data insert value. register value is inserted into the stm-1(au-4) output c2 byte. 0x00 address dec (hex) bit name function reset default 71 (0x47) 7?0 tf2dins [7:0] transmit f2 data insert value. register value is inserted into the stm-1(au-4) output f2 byte. 0x00 address dec (hex) bit name function reset default 72 (0x48) 7?0 tz3dins[7:0] transmit z3 data insert value. register value is inserted into the stm-1(au-4) output z3 byte. 0x00
agere systems inc. 71 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) register map (continued) table 48. register 73: tandem connection byte (r/w) table 49. register 74: transmit high-speed line rdi insertion inhibit bits (r/w) table 50. register 75: transmit high-speed path rdi insertion inhibit bits (r/w) address dec (hex) bit name function reset default 73 (0x49) 7?0 tz5dins[7:0] transmit z5 data insert value. register value is inserted into the stm-1(au-4) output z5 byte. 0x00 address dec (hex) bit name function reset default 74 (0x4a) 7 tlrdiinh transmit rdi-l inhibit control. control bit, when set to a logic 0, allows software to insert the tk2ins[2:0] byte, 0x43 into the outgoing k2[2:0] bits; otherwise, line rdi 110 is inserted if the appropriate alarms are active. 1 74 (0x4a) 5 trhssf_lrdiinh transmit receive high-speed signal fail l-rdi inhibit. control bits, when set to a logic 1, causes the associated failure not to contribute to the auto- matic insertion of rdi-l; otherwise, the associated alarm contributes to the generation of rdi-l. 0 74 (0x4a) 4 trlaismon_lrdiinh transmit receive line ais path rdi inhibit. same as above. 0 74 (0x4a) 3 trhslof_lrdiinh transmit receive high-speed loss-of-frame line rdi inhibit. same as above. 1 74 (0x4a) 2 trhsoof_lrdiinh transmit receive high-speed out-of-frame line rdi inhibit. same as above. 0 74 (0x4a) 1 trhslos_lrdiinh transmit receive high-speed loss-of-signal line rdi inhibit. same as above. 0 74 (0x4a) 0 triloc_lrdiinh transmit receive input loss-of-clock line rdi inhibit. same as above. 0 address dec (hex) bit name function reset default 75 (0x4b) 7 tprdiins transmit rdi-p insert. control bit, when set to a logic 1, allows software to insert p-rdi into the out- going g1[3] bit, au-4 mode only; otherwise, insert path rdi under hardware control. 0 75 (0x4b) 6 trlop1_prdiinh transmit receive loss-of-pointer path rdi inhibit. control bits, when set to a logic 1, causes the associated failure not to contribute to the auto- matic insertion of rdi-p; otherwise, the associated alarm contributes to the generation of rdi-p (port 1, au-4 mode only). 0 75 (0x4b) 5 trpais1_prdiinh transmit receive path ais path rdi inhibit. same as above. 0
72 72 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) register map (continued) table 50. register 75: transmit high-speed path rdi insertion inhibit bits (r/w) (continued) table 51. register 76: transmit high-speed error insert control parameters (r/w) address dec (hex) bit name function reset default 75 (0x4b) 4 trlaismon_prdiinh transmit receive line ais path rdi inhibit. same as above. 0 75 (0x4b) 3 trhslof_prdiinh transmit receive high-speed loss-of-frame path rdi inhibit. same as above. 1 75 (0x4b) 2 trhsoof_prdiinh transmit receive high-speed out-of-frame path rdi inhibit. same as above. 0 75 (0x4b) 1 trhslos_prdiinh transmit receive high-speed loss-of- signal path rdi inhibit. same as above. 0 75 (0x4b) 0 triloc_prdiinh transmit receive input loss-of-clock path rdi inhibit. same as above. 0 address dec (hex) bit name function reset default 76 (0x4c) 4 thsb3errins transmit high-speed b3 error insert. control bit, when set to a logic 1, causes the output b3 byte in the outgoing stm-1 (au-4) signal to be inverted. 0 76 (0x4c) 3?1 thsb2errins[3?1] transmit high-speed b2 error insert. control bit, when set to a logic 1, causes the output b2 bytes in the outgoing sts-3/stm-1 (au-4) signal to be inverted. 000 76 (0x4c) 0 thsb1errins transmit high-speed b1 error insert. control bit, when set to a logic 1, causes the output b1 byte in the outgoing sts-3/stm-1 (au-4) signal to be inverted. 0
agere systems inc. 73 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) register map (continued) table 52. register 77: transmit high-speed error insert control parameters (r/w) table 53. register 78: transmit high-speed error insert (r/w) address dec (hex) bit name function reset default 77 (0x4d) 7 tpfebeeins transmit path febe error insert. control bit, when set to a logic 1, causes a continuous path febe error in the outgoing stm-1 (au-4) signal; otherwise, a normal path febe value is sent. 0 77 (0x4d) 6 tsfebeeins transmit section febe error insert. control bit, when set to a logic 1, causes a continuous section febe error in the outgoing sts-3/stm-1 (au-4) signal; otherwise, the normal section febe value is sent. 0 77 (0x4d) 5 tapsbableins transmit aps babble insert. control bit, when set to a logic 1, causes an inconsistent aps byte (k1[7:0], k2[7:3]) to be inserted into the outgoing sts-3/stm-1 (au-4) frame. 0 77 (0x4d) 4?0 ta1a2errins[4:0] transmit frame error insert value. these bits specify the number of consecutive frames to be inserted with a frame error (a1a2). this register is used in conjunction with control bit ta1a2erren, 0x04. 0x0 address dec (hex) bit name function reset default 78 (0x4e) 7?5 th1h2crupen[3?1] transmit h1 h2 corrupt enable. control bits, when set to a logic 1, cause the output h1 and h2 bytes of the sts-3/stm-1 (au-4) signal to be cor- rupted on a per sts-1 basis. in the au-4 mode, only control bit 1 is used. 000 78 (0x4e) 4 th1h2crupporndf transmit h1 h2 corrupt or ndf. control bit, when set to a logic 0, causes an invalid pointer to be inserted into the output h1 and h2 bytes; otherwise, a continuous ndf condition (1001) is sent. 0 78 (0x4e) 2 tpat23or15 transmit test pattern (2 23 ? 1) or (2 15 ? 1). control bit, when set to a logic 0, causes a q23 + q17 +1 pattern to be inserted; otherwise, generate a q15 + q14 + 1 pattern. 0 78 (0x4e) 1?0 tstgen_psel[1:0] transmit test generation port select. control bits specify which tug-3 the pseudorandom pat- tern is inserted into: 00 disable, 01 = tug-3 #1, 10 = tug-3 #2, 11 = tug-3 #3. 00
74 74 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) register map (continued) table 54. register 79: receive/transmit toac control (r/w) address dec (hex) bit name function reset default 79 (0x4f) 7 rtoac_clkinv receive toac clock invert control. control bit, when set to a logic 1, forces the receive toac clock to be inverted leaving the device; otherwise, the clock is not inverted. 0 79 (0x4f) 6 rtoacs_a1orend receive toac sync a1 or frame-end align. control bit, when set to a logic 0, forces the output 8 khz frame sync signal to be aligned with the first bit of the frame; otherwise, align the output 8 khz frame sync with the last bit of the previous frame. 0 79 (0x4f) 5 rtoac_oepins receive toac odd or even parity insert. control bit, when set to a logic 1, forces the output toac parity bit to be even; otherwise, the parity is odd. 0 79 (0x4f) 4 rtoacinh receive toac clock/sync/data inhibit. control bit, when set to a logic 1, forces the receive toac clock, sync, and data outputs to be placed in a high- impedance state. 0 79 (0x4f) 3 ttoac_clkinv transmit toac clock invert control. control bit, when set to a logic 1, forces the output clock to be inverted leaving the device; otherwise, the clock is not inverted. 0 79 (0x4f) 2 ttoacsa1orend transmit toac sync a1 or frame-end align. control bit, when set to a logic 0, forces the output 8 khz frame sync signal to be aligned with the first bit of the frame; otherwise, align the output 8 khz frame sync with the last bit of the previous frame. 0 79 (0x4f) 1 ttoac_oepmon transmit toac odd or even parity monitor. control bit, when set to a logic 1, forces the input toac parity checker to check for odd parity; other- wise, even parity is checked on the transmit toac channel. 0 79 (0x4f) 0 ttoacinh transmit toac clock and sync inhibit. control bit, when set to a logic 1, forces the transmit toac clock and sync to be placed in a high-impedance state. 0
agere systems inc. 75 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) register map (continued) table 55. registers 80, 81: transmit toac control (r/w) address dec (hex) bit name function reset default 80 (0x50) 7?6 ttoac_e2[1:0] transmit toac e2 byte control. control bits, when set to a logic 00 or 11, cause the default value to be inserted into the e2 byte in the transmit sts- 3/stm-1 (au-4) frame. setting these control bits to a logic 01 causes the ttoac value to be inserted into the e2 byte. setting these control bits to a logic 10 causes the e2 value in the associated sts-1/ au-3 to pass through unchanged. 00 80 (0x50) 5?4 ttoac_e1[1:0] transmit toac e1 byte control. control bits, when set to a logic 00 or 11, cause the default value to be inserted into the e1 byte in the transmit sts- 3/stm-1 (au-4) frame. setting these control bits to a logic 01 causes the ttoac value to be inserted into the e1 byte. setting these control bits to a logic 10 causes the e1 value in the associated sts-1/ au-3 to pass through unchanged. 00 80 (0x50) 3?2 ttoac_d4to12[1:0] transmit toac d4 to d12 byte control. control bits, when set to a logic 00 or 11, cause the default value to be inserted into the d4 to d12 bytes in the transmit sts-3/stm-1 (au-4) frame. setting these control bits to a logic 01 causes the ttoac values to be inserted into the d4 to d12 bytes, respec- tively. setting these control bits to a logic 10 causes the d4 to d12 values in the associated sts-1/au-3 to pass through unchanged. 00 80 (0x50) 1?0 ttoac_d1to3[1:0] transmit toac d1 to d12 byte control. control bits, when set to a logic 00 or 11, cause the default value to be inserted into the d1 to d3 bytes in the transmit sts-3/stm-1 (au-4) frame. setting these control bits to a logic 01 causes the ttoac values to be inserted into the d1 to d3 bytes, respectively. setting these control bits to a logic 10 causes the d1 to d3 values in the associated sts-1/au-3 to pass through unchanged. 00
76 76 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) register map (continued) table 55. registers 80, 81: transmit toac control (r/w) (continued) address dec (hex) bit name function reset default 81 (0x51) 7?6 ttoac_ins[1:0] transmit toac byte control. control bits, when set to a logic 00 or 11, cause the default value to be inserted into all overhead bytes without specific insert control bits in the transmit sts-3/stm-1 (au-4) frame. setting these control bits to a logic 01 causes the ttoac value to be inserted into all overhead bytes without specific insert control bits. setting these control bits to a logic 10 causes the associated sts-1/au-3 values to pass through unchanged. 00 81 (0x51) 5?4 ttoac_z2[1:0] transmit toac z2 byte control. control bits, when set to a logic 00 or 11, cause the default value to be inserted into the z2 byte in the transmit sts-3/stm-1 (au-4) frame. setting these control bits to a logic 01 causes the ttoac value to be inserted into the z2 byte. setting these control bits to a logic 10 causes the z2 value in the associated sts-1/au-3 to pass through unchanged. 00 81 (0x51) 3?2 ttoac_z1[1:0] transmit toac z1 byte control. control bits, when set to a logic 00 or 11, cause the default value to be inserted into the z1 byte in the transmit sts-3/stm-1 (au-4) frame. setting these control bits to a logic 01 causes the ttoac value to be inserted into the z1 byte. setting these control bits to a logic 10 causes the z1 value in the associated sts-1/au-3 to pass through unchanged. 00 81 (0x51) 1?0 ttoac_f1[1:0] transmit toac f1 byte control. control bits, when set to a logic 00 or 11, cause the default value to be inserted into the f1 byte in the transmit sts-3/stm-1 (au-4) frame. setting these control bits to a logic 01 causes the ttoac value to be inserted into the f1 byte. setting these control bits to a logic 10 causes the f1 value in the associated sts-1/au-3 to pass through unchanged. 00
agere systems inc. 77 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) register map (continued) table 56. register 83, 84: transmit high-speed sts-3/stm-1 output frame offset (r/w) ths sync/data alignment equations and tables equations for sync alignment: x = desired row y = desired column r, c, s, b, rmult, and cmult (see table 57, a1-1 alignment parameters.) equation 1. (((x ? rmult) + (y ? cmult))/cmult) ? 1/90 = rowsub + colsub/90 equation 2. rparm = r ? rowsub equation 3. cparm = c ? colsub equation 4. if (x = 8) then if (cparm = ?2) then tlrowcnt = 8 tlcolcnt = 88 else if (cparm = ?1) then tlrowcnt = 8 tlcolcnt = 89 else if (x | 8) then if (cparm = ?2) then tlrowcnt = rparm ? 1 tlcolcnt = 88 else if (cparm = ?1) then tlrowcnt = rparm ? 1 tlcolcnt = 89 address dec (hex) bit name function reset default 83 (0x53) 7?5 tlbitcnt[2:0] transmit load bit count. allow the output sts-3/ stm-1 (au-4) frame to have any relationship to the input j0 frame sync pulse (thssj0j1v1i (t/c)). the actual operation of these registers is listed below. 000 83 (0x53) 84 (0x54) 3?0 7?4 tlcolcnt[6:4] tlcolcnt[3:0] transmit load column count. same as above. 0000000 83 (0x53) 4?3 tlsts1cnt[1:0] transmit load sts1 count. same as above. 00 84 (0x54) 2?0 tlrowcnt[3:0] transmit load row count . same as above. 0000
78 78 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) register map (continued) otherwise tlrowcnt = rparm tlcolcnt = cparm equation 5. if (thsclktype = bit and thsptype = bit) tlbitcnt = (selected bit from bitcnt alignment table, table 58 on page 80.) otherwise tlbitcnt = b equation 6. if (thsclktype = bit and thsptype = bit and b 7) tlsts1cnt = s ? 1 (i.e., 0 2, 1 0, 2 1) if (sts #2) then tlcolcnt = tlcolcnt ? 1 else tlcolcnt = tlcolcnt if (y = 89 and sts #2 and tlrowcnt = 0) then tlrowcnt = 8 else if (y = 89 and sts #2) then tlrowcnt = tlrowcnt ? 1 else tlrowcnt = tlrowcnt otherwise tlsts1cnt = s examples 1. align sync with d3, sts #1, thsclktype = byte, thsptype = byte x = 2, y = 2 (from table 57, a1-1 alignment parameters) (((2 ? 270) + (2 ? 3))/3) ? 1/90 = 2 + 2/90 (equation #1) rparm = 8 ? 2 = 6 (equation #2) cparm = 87 ? 2 = 85 (equation #3) tlrowcnt = 6 (equation #4) tlcolcnt = 86 (equation #4) tlbitcnt = 0 (equation #5) tlsts1cnt = 2 (equation #6)
agere systems inc. 79 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) register map (continued) 2. align sync with row = 8, column = 89, sts #3 thsclktype = byte, thsptype = byte x = 8, y = 89 (from table 57, a1-1 alignment parameters) (((8 ? 270) + (89 ? 3))/3) ? 1/90 = 8 + 89/90 (equation #1) rparm = 8 ? 8 = 0 (equation #2) cparm = 87 ? 89 = ?2 (equation #3) tlrowcnt = 8 (equation #4) tlcolcnt = 88 (equation #4) tlbitcnt = 0 (equation #5) tlsts1cnt = 0 (equation #6) 3. align sync with row = 5, column = 89, sts #3 thsclktype = nibble, thsptype = byte x = 5, y = 89 (from table 57, a1-1 alignment parameters) (((5 ? 540) + (89 ? 6))/6) ? 1/90 = 5 + 89/90 (equation #1) rparm = 8 ? 5 = 3 (equation #2) cparm = 88 ? 89 = ?1 (equation #3) tlrowcnt = 3 ? 1 = 2 (equation #4) tlcolcnt = 89 (equation #4) tlbitcnt = 0 (equation #5) tlsts1cnt = 1 (equation #6)
80 80 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) register map (continued) table 57. a1-1 alignment parameters * aligns with msn. table 58. bitcnt alignment table valid for thsclktype = thsptype only. thsclktype thsptype sts # r c s b rmult cmult bit bit bit bit bit bit 1 2 3 8 8 8 89 89 88 1 0 2 7 7 7 2160 2160 2160 24 24 24 bit bit bit nibble nibble nibble 1 2 3 8 8 8 89 89 88 1 0 2 6* 6* 6* 2160 2160 2160 24 24 24 bit bit bit byte byte byte 1 2 3 8 8 8 89 89 88 1 0 2 6 6 6 2160 2160 2160 24 24 24 nibble nibble nibble nibble nibble nibble 1 2 3 8 8 8 88 88 88 2 1 0 1 1 1 540 540 540 6 6 6 nibble nibble nibble byte byte byte 1 2 3 8 8 8 88 88 88 2 1 0 1 1 1 540 540 540 6 6 6 byte byte byte byte byte byte 1 2 3 8 8 8 87 87 87 2 1 0 0 0 0 270 270 270 3 3 3 msb lsb a1-1 byte a1 bit 7 a1 bit 6 a1 bit 5 a1 bit 4 a1 bit 3 a1 bit 2 a1 bit 1 a1 bit 0 bit b = 7b = 0b = 1b = 2b = 3b = 4b = 5b = 6 nibble (msn) b = 1 (lsn) b = 0 byte b = 0
agere systems inc. 81 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) register map (continued) table 59. register 85: receive high/low-speed port control (r/w) address dec (hex) bit name function reset default 85 (0x55) 7 ths2rhslb transmit high-speed receive high-speed loopback control. control bit, when set to a logic 1, causes the transmit output sts-3/stm-1 (au-4) signal to be looped back to the receive input; other- wise, the loopback is disabled. 0 85 (0x55) 6 rhsdscr receive high-speed descramble enable. control bit, when set to a logic 1, causes the input sts-3/ stm-1 (au-4) signal to be descrambled; otherwise, the signal is not descrambled. 0 85 (0x55) 5 rconcatmode receive concatenation mode. control bit, when set to a logic 1, causes the input pointer interpreter to operate in concatenation mode. this mode is most likely used in the au-4 mode; otherwise, three independent pointers are expected. 0 85 (0x55) 4 rrdi_mpyorefc receive rdi monitor path yellow or enhanced failure code. control bit, when set to a logic 0, causes the device to monitor path yellow in the incoming g1 byte bit 3; otherwise, the device moni- tors for an enhanced failure code in the g1 byte bits 3 down to 1. 0 85 (0x55) 3 rhsvoepar receive high-speed verify odd or even parity. control bit when, set to a logic 0, causes odd parity to be verified in nibble/parallel mode per clock transfer on the sts-3/stm-1 (au-4) input; other- wise, even parity is verified. 0 85 (0x55) 2 rhsedge receive high-speed retime edge control. con- trol bit, when set to a logic 1, causes the sts-3/ stm-1 (au-4) input data to be retimed on the posi- tive edge; otherwise, the input sts-3/stm-1 (au-4) input data is retimed on the falling edge of the input clock. 0 85 (0x55) 1?0 rhsptype[1:0] receive high-speed port type. control bits are used to control the type of output interface required: 00 = serial interface, 01 = nibble interface, 10 = byte-wide interface. 00
82 82 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) register map (continued) table 60. register 86: receive j1 and receive low-speed port select control (r/w) table 61. register 87: sts-1/au-3 receive control bits (r/w) address dec (hex) bit name function reset default 86 (0x56) 7?6 j1pselmon[1:0] j1 port select monitor control. control bits are used to select which j1 byte will be monitored in the received sts-3/stm-1 (au-4) signal: 00 = port 1, 01 = port 2, 10 = port 3, 11 = undefined operation. 00 86 (0x56) 5?4 3?2 1?0 rsel[3?1][1:0] receive port select control. control bits allow receive output selection: 00 or 11 = port 1 selected, 01 = port 2 selected, 10 = port 3 selected. 10 01 00 address dec (hex) bit name function reset default 87 (0x57) 7?5 rlsscr[3?1] receive low-speed scrambler enable. control bit, when set to a logic 1, causes the selected sts-1/au-3 output signal to be scrambled; other- wise, the output signal is not scrambled. 000 87 (0x57) 4 rhsporcdrsel receive high-speed port or cdr clock and data select. control bit, when set to a logic 0, causes the differential receive clock and data inputs (rhssclkit/c, rhssdatait/c) to be used in the device receive path; otherwise, the outputs of the cdr clock recovery block are used. 0 87 (0x57) 3 paislop_aisinh path ais or lop ais inhibit. control bit, when set to a logic 0, causes state bits pais and lop to con- tribute to the generation of path ais; otherwise, the state bits are inhibited from contributing to path ais generation. 0 87 (0x57) 2 tls2rlslb transmit low-speed to receive low-speed loopback. control bit, when set to a logic 1, causes the transmit sts-1/au-3 input signals to be looped back to the receive sts-1/au-3 outputs; otherwise, loopback is disabled. 0 87 (0x57) 1 rlsclkinv receive low-speed clock invert control. con- trol bit, when set to a logic 1, causes the output clock to be inverted; otherwise, the output sts-1/ au-3 receive clock is not inverted. 0 87 (0x57) 0 rlsparoeg receive low-speed parity odd or even genera- tion. control bit, when set to a logic 1, forces the output parity bit to be even; otherwise, the parity is odd. 0
agere systems inc. 83 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) register map (continued) table 62. register 88: sts-1/au-3 receive low-speed ais inhibit control bits (r/w) table 63. registers 88, 89: sts-1/au-3 loss of signal detector (r/w) table 64. register 90?95: continuous n times detect (cntd) values (r/w) address dec (hex) bit name function reset default 88 (0x58) 7 rrlaismon_aisinh receive line ais monitor ais inhibit. control bits, when set to a logic 1, inhibit the associated alarm from causing ais generation; otherwise, these allow the associated failure to cause ais gen- eration on all sts-1/au-3 outputs. 0 88 (0x58) 6 rrhslos_aisinh receive high-speed loss-of-signal ais inhibit. same as above. 0 88 (0x58) 5 rrhslof_aisinh receive high-speed loss-of-frame ais inhibit. same as above. 1 88 (0x58) 4 rrhsoof_aisinh receive high-speed out-of-frame ais inhibit. same as above. 0 88 (0x58) 3 rriloc_aisinh receive input loss-of-clock ais inhibit. same as above. 0 address dec (hex) bit name function reset default 88 (0x58) 89 (0x59) 2?0 7?0 losdetcnt[10:8] losdetcnt[7:0] loss-of-signal detection count. control bits are the number of consecutive all-zeros/-ones pattern detected to declare los state in the unscrambled sts-3/stm-1 (au-4) input frame. a value of 0x02d equals 2.3 s while a value of 0x798 equals 100 s. 0x02d = 2.3 s address dec (hex) bit name function reset default 90 (0x5a) 7?4 cntdf1[3:0] continuous n times detect for f1 byte. register sets the number of cntd occurrences of a consis- tent f1 value in the incoming sts-3/stm-1 (au-4) frame. the valid range for this register is 0x3?0xf. invalid values will be mapped to a value of 0x3. 0x3 90 (0x5a) 3?0 cntdj0z0[3:0] continuous n times detect for j0z0 bytes. reg- ister sets the number of cntd occurrences of a consistent j0, z0-2, and z0-3 values in the incom- ing sts-3/stm-1 (au-4) frame. the valid range for this register is 0x3?0xf. invalid values will be mapped to a value of 0x3. 0x3
84 84 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) register map (continued) table 64. register 90?95: continuous n times detect (cntd) values (r/w) (continued) address dec (hex) bit name function reset default 91 (0x5b) 7?4 cntdaps[3:0] continuous n times detect for aps (k1, k2[7:3]) byte. register sets the number of cntd occurrences of a consistent aps value in the incoming sts-3/stm-1 (au-4) frame. the valid range for this register is 0x3?0xf. invalid values will be mapped to a value of 0x3. 0x3 91 (0x5b) 3?0 cntdk2[3:0] continuous n times detect for k2[2:0] byte. register sets the number of cntd occurrences of a consistent k2[2:0] value in the incoming sts-3/ stm-1 (au-4) frame. the valid range for this regis- ter is 0x3?0xf. invalid values will be mapped to a value of 0x3. 0x3 92 (0x5c) 7?4 cntdapsframe[3:0] continuous n times detect for aps frame byte. register sets the number of cntd frames that an inconsistent aps value in the incoming sts-3/ stm-1 (au-4) frame detects. this value is used in the aps babble algorithm. the valid range for this register is 0x3?0xf. invalid values will be mapped to a value of 0x3. 0xc 92 (0x5c) 3?0 cntds1[3:0] continuous n times detect for s1 byte. register sets the number of cntd occurrences of a consis- tent s1 value in the incoming sts-3/stm-1 (au-4) frame. the valid range for this register is 0x3?0xf. invalid values will be mapped to a value of 0x3. 0x3 93 (0x5d) 7?4 cntdg1[3:0] continuous n times detect for g1 byte. register sets the number of cntd occurrences of a consis- tent g1 value in the incoming sts-3/stm-1 (au-4) frame. the valid range for this register is 0x3?0xf. invalid values will be mapped to a value of 0x3. 0x3 93 (0x5d) 3?0 cntdc2[3:0] continuous n times detect for c2 byte. register sets the number of cntd occurrences of a consis- tent c2 value in the incoming sts-3/stm-1 (au-4) frame. the valid range for this register is 0x3?0xf. invalid values will be mapped to a value of 0x3. 0x3 94 (0x5e) 7?4 cntdf2[3:0] continuous n times detect for f2 byte. register sets the number of cntd occurrences of a consis- tent f2 value in the incoming sts-3/stm-1 (au-4) frame. the valid range for this register is 0x3?0xf. invalid values will be mapped to a value of 0x3. 0x3
agere systems inc. 85 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) register map (continued) table 64. register 90?95: continuous n times detect (cntd) values (r/w) (continued) table 65. register 95: continuous n times detect (cntd) b1 control bit (r/w) address dec (hex) bit name function reset default 94 (0x5e) 3?0 cntdz3[3:0] continuous n times detect for z3 byte. register sets the number of cntd occurrences of a consistent z3 value in the incoming sts-3/stm-1 (au-4) frame. the valid range for this register is 0x3?0xf. invalid values will be mapped to a value of 0x3. 0x3 95 (0x5f) 3?0 cntdz5[3:0] continuous n times detect for z5 byte. register sets the number of cntd occurrences of a consistent z5 value in the incoming sts-3/stm-1 (au-4) frame. the valid range for this register is 0x3?0xf. invalid values will be mapped to a value of 0x3. 0x3 address dec (hex) bit name function reset default 95 (0x5f) 7 cntdb1sel continuous n times detect b1 select. control bit, when set to a logic 1, causes the k2 byte cntd mon- itors to be reset whenever a b1 error occurs; other- wise, b1 errors are ignored. 0 95 (0x5f) 6 rlocinh receive loss-of-clock inhibit. control bit, when set to a logic 1, inhibits the device receive path from using the transmit high-speed clock during an riloc, 0x1b condition (ais generation); otherwise, automati- cally switch to the transmit clock during a riloc con- dition. 0 95 (0x5f) 5?4 cntcip_ici[1:0] continuous n times detect invalid pointer and invalid concatenation indication. control bits are the number of consecutive conditions for invalid pointer and invalid concatenation indication (pointer interpretation). valid values are the following: 00 = 8\d, 01 = 9\d, 10 = 10\d, and 11 = 8\d. 00
86 86 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) register map (continued) table 66. register 96: test pattern drop control and status table 67. register 97: test pattern drop error counter (ro) table 68. register 98: receive low-speed overhead control bits (r/w) address dec (hex) bit name function reset default 96 (0x60) 7 rtstdrp_oos receive test drop out-of-sync indication (ro). state bit, when at a logic 1, indicates the test pat- tern is out of sync (oos); a logic 0 indicates the test pattern monitor is in sync and able to count bit errors in the pseudorandom test pattern. 1 96 (0x60) 2 rpat23or15 receive test drop pattern detect (2 23 ? 1) or (2 15 ? 1) (r/w). control bit, when set to a logic 0, causes a q23 + q17 + 1 pattern to be monitored; otherwise, a q15 + q14 + 1 pattern is monitored. 0 96 (0x60) 1?0 rtstdrp_psel[1:0] receive test drop port select control (r/w). control bits specify which tug-3 the pseudoran- dom pattern is to be monitored: 00 disable, 01 = tug-3 #1, 10 = tug-3 #2, 11 = tug-3 #3. 00 address dec (hex) bit name function reset default 97 (0x61) 7?0 rtstdrp_ecnt[7:0] receive test drop error count. value counts the number of errors received on the monitored pseu- dorandom signal. this counter will hold at its maxi- mum value. 0x00 address dec (hex) bit name function reset default 98 (0x62) 7?5 ra1a2errpen[3?1] receive a1a2 error insert port enables . port into which framing errors will be injected. the num- ber of consecutive frames that contain errors is con- trolled by ra1a2errins[4:0] in the same register in which the action takes place when ra1a2erren, 0x04 transitions from a logic 0 to logic 1. 000 98 (0x62) 4?0 ra1a2errins[4:0] receive a1a2 frame error insert. same as above. 0x1
agere systems inc. 87 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) register map (continued) table 69. register 99: receive low-speed bip error insert (r/w) table 70. registers 100?102: receive low-speed overhead control bits (r/w) address dec (hex) bit name function reset default 99 (0x63) 5?3 rb2errins[3?1] receive b2 error insert control. control bit, when set to a logic 1, causes the respective b2 byte in the outgoing sts-1/au-3 signal to be inverted. 000 99 (0x63) 2?0 rb1errins[3?1] receive b1 error insert control. control bit, when set to a logic 1, causes the respective b1 byte in the outgoing sts-1/au-3 signal to be inverted. 000 address dec (hex) bit name function reset default 100 (0x64) 6 rh1h2crupporndf receive h1 h2 corrupt or ndf. control bit, when set to a logic 0, causes an invalid pointer to be inserted into the output h1 and h2 bytes; otherwise, a continuous ndf condition (1001) is forced in the sts-1/au-3 signal. 0 100 (0x64) 5?3 rh1h2crupen[3?1] receive h1 h2 corrupt enable. control bits, when set to a logic 1, causes the output h1 and h2 bytes of the sts-1/au-3 signal to be corrupted as con- trolled by register bit rh1h2crupporndf in the same register. 000 100 (0x64) 2?0 rf1ins[3?1] receive f1 data insert. control bits, when set to a logic 1, causes the rf1dins[3?1][7:0], 0x6b?6d values to be inserted into the respective output f1 bytes in the sts-1/au-3 signals; otherwise, insert the value set by the r_f1_pass[3?1] control bit, 0x74. 000 101 (0x65) 5?3 rsfebeerrins[3?1] receive section febe error insert. control bit, when set to a logic 1, causes a section febe (b2 error value of 0x3) to be inserted into the sts-1/ au-3 output signal; otherwise, an error is not inserted. 000 101 (0x65) 2?0 rsfebeinh[3?1] receive section febe hardware inhibit. control bit, when set to a logic 1, inhibits the hardware insert of section febe in the sts-1/au-3 output signal; otherwise, the default value is inserted. 000 102 (0x66) 5?3 rlaisins[3?1] receive line ais insert. control bit, when set to a logic 1, forces l-ais to be inserted into the outgoing sts-1/au-3 frame. 000 102 (0x66) 2?0 rapsbableins[3?1] receive aps babble insert. control bit, when set to a logic 1, causes an inconsistent aps byte (k1[7:0], k2[7:3]) to be inserted into the outgoing sts-1/au-3 frame. 000
88 88 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) register map (continued) table 71. register 103: receive low-speed l-rdi inhibit control (r/w) table 72. registers 104?106: receive low-speed c1 byte (r/w) table 73. registers 107?109: receive low-speed f1 byte (r/w) table 74. registers 110?115: receive low-speed k1, k2 byte insert (r/w) address dec (hex) bit name function reset default 103 (0x67) 6 rtiloc_lrdiinh receive transmit input loss-of-clock rdi-l inhibit. control bits, when set to a logic 1, inhibit the associated alarm from contributing to rdi-l generation per sts-1/au-3 frame. 0 103 (0x67) 5?3 rtlslof_lrdiinh[3?1] receive transmit low-speed loss-of-frame rdi-l inhibit. same as above. 111 103 (0x67) 2?0 rtlsoof_lrdiinh[3?1] receive transmit low-speed out-of-frame rdi-l inhibit. same as above. 000 address dec (hex) bit name function reset default 104 (0x68) 105 (0x69) 106 (0x6a) 7?0 rc1dins[1?3][7:0] receive c1 data insert. register value is inserted into the respective sts-1/au-3 output c1 byte. 0x00 address dec (hex) bit name function reset default 107 (0x6b) 108 (0x6c) 109 (0x6d) 7?0 rf1dins[1?3][7:0] receive f1 software insert. register value is inserted into the respective sts-1/au-3 output f1 byte. 0x00 address dec (hex) bit name function reset default 110 (0x6e) 111 (0x6f) 7?3 7?0 rapsins1[12:8] rapsins1[7:0] receive aps insert. register value is inserted into the respective sts-1/au-3 output k1 and k2[7:3] bytes. 0x0000 112 (0x70) 113 (0x71) 7?3 7?0 rapsins2[12:8] rapsins2[7:0] 114 (0x72) 115 (0x73) 7?3 7?0 rapsins3[12:8] rapsins3[7:0] 110 (0x6e) 112 (0x70) 114 (0x72) 2?0 rk2dins[3?1][2:0] receive k2 data insert. register value is inserted into the respective sts-1/au-3 output k2[2:0] bits. 000
agere systems inc. 89 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) register map (continued) table 75. registers 116?118: receive low-speed pass control (r/w) address dec (hex) bit name function reset default 116 (0x74) 5?3 r_f1_pass[3?1] receive f1 pass. control bit, when set to a logic 1, allows the associated sts-3/stm-1 (au-4) f1 byte to pass unchanged to the sts-1/au-3 out- put signal; otherwise, the default value is inserted. 000 116 (0x74) 2?0 r_e1_pass[3?1] receive e1 pass. control bit, when set to a logic 1, allows the associated sts-3/stm-1 (au-4) e1 byte to pass unchanged to the sts-1/au-3 out- put signal; otherwise, the default value is inserted. 000 117 (0x75) 5?3 r_d4tod12_pass[3?1] receive d4 to d12 pass. control bit, when set to a logic 1, allows the associated sts-3/stm-1 (au-4) d4 to d12 bytes to pass unchanged to the sts-1/au-3 output signal; otherwise, the default value is inserted. 000 117 (0x75) 2?0 r_d1tod3_pass[3?1] receive d1 to d3 pass. control bit, when set to a logic 1, allows the associated sts-3/ stm-1(au-4) d1 to d3 bytes to pass unchanged to the sts-1/au-3 output signal; otherwise, the default value is inserted. 000 118 (0x76) 5?3 r_e2_pass[3?1] receive e2 pass. control bit, when set to a logic 1, allows the associated sts-3/stm-1 (au-4) e2 byte to pass unchanged to the sts-1/au-3 out- put signal; otherwise, the default value is inserted. 000 118 (0x76) 2?0 r_s1_pass[3?1] receive s1 pass. control bit, when set to a logic 1, allows the associated sts-3/stm-1 (au-4) s1 byte to pass unchanged to the sts-1/au-3 out- put signal; otherwise, the default value is inserted. 000
90 90 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) register map (continued) table 76. register 127: page control register (r/w) table 77. page 0 - registers 128?191: j1 insert parameters (r/w) table 78. page 0 - registers 192?255: j1 monitor bytes (ro) table 79. page 1 - registers 128?133: sts-1/au-3 b1 bip error counters (ro) address dec (hex) bit name function reset default 127 (0x7f) 1?0 page[1:0] page number. control bits select the page accessed when an address greater than 128 is accessed: 00 = page 0 (j1 byte insert/monitor), 01 = page 1 (error counters), 10 = page 2 (ber algorithm parameters), 11 = illegal value. 00 address dec (hex) bit name function reset default 128 (0x80)? 191 (0xbf) 7?0 tj1dins[64?1][7:0] transmit j1 data insert. registers allow a 64-byte sequence to be inserted into the j1 byte of the stm-1(au-4) output signal. 0x00 address dec (hex) bit name function reset default 192 (0xc0)? 255 (0xff) 7?0 rj1mon[64?1][7:0] receive j1 monitor data. registers capture a 64-byte sequence from the selected (j1pselmon[1:0], 0x56) j1 byte of the sts-3/ stm-1 (au-4) input signal. 0x00 address dec (hex) bit name function reset default 128 (0x80)? 133 (0x85) 7?0 tlsb1ecnt[1?3][15:8] tlsb1ecnt[1?3][7:0] transmit low-speed b1 error count. these are the b1 bip error rate counters. these counters can either count actual bip errors or block errors (bitblockcnt, 0x34). these counters hold at their maximum values and trans- fer their internal counts to a holding register when latch_cnt, 0x04 transitions from a logic 0 to 1. 0x0000
agere systems inc. 91 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) register map (continued) table 80. page 1 - registers 134?140: sts-1/au-3 b2 bip error counters (ro) table 81. page 1 - registers 141?142: sts-3/stm-1 (au-4) b1 error count (ro) table 82. page 1 - registers 143?145: sts-3/stm-1 (au-4) b2 error count (ro) address dec (hex) bit name function reset default 137 (0x89)? 140 (0x8c) 7?0 tlsb2ecnt[2?3][15:8] tlsb2ecnt[2?3][7:0] transmit low-speed b2 error count ports 2 and 3. these are the b2 bip error rate counters. these counters can either count actual bip errors or block errors (bitblockcnt , 0x34). these counters hold at their maximum values and trans- fer their internal counts to a holding register when latch_cnt, 0x04 transitions from a logic 0 to 1. 0x0000 134 (0x86) 135 (0x87) 136 (0x88) 1?0 7?0 7?0 tlsb2ecnt[1][17:16] tlsb2ecnt[1][15:8] tlsb2ecnt[1][7:0] transmit low-speed b2 error count port 1. same as above. 0x00000 address dec (hex) bit name function reset default 141 (0x8d) 142 (0x8e) 7?0 rhsb1ecnt[15:8] rhsb1ecnt[7:0] receive high-speed b1 error count. counts the number of b1 errors in the received sts-3/ stm-1 (au-4) frame. this counter can either count actual bip errors or block errors (bitblockcnt, 0x34). this counter holds at its maximum value and transfers its internal count to a holding register when latch_cnt, 0x04 tran- sitions from a logic 0 to 1. 0x0000 address dec (hex) bit name function reset default 143 (0x8f) 144 (0x90) 145 (0x91) 1?0 7?0 7?0 rhsb2ecnt[17:16] rhsb2ecnt[15:8] rhsb2ecnt[7:0] receive high-speed b2 error count. counts the number of b2 errors in the received sts-3/ stm-1 (au-4) frame. this counter can either count actual bip errors or block errors (bitblockcnt, 0x34). this counter holds at its maximum value and transfers its internal count to a holding register when latch_cnt, 0x04 tran- sitions from a logic 0 to 1. 0x00000
92 92 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) register map (continued) table 83. page 1 - registers 146?151: sts-3/stm-1 (au-4) b3 error count (ro) table 84. page 1 - registers 152?163: sts-3/stm-1 (au-4) pointer increment/decrement counter (ro) table 85. page 1 - registers 164?166: receive high-speed sfebe count (ro) address dec (hex) bit name function reset default 146 (0x92)? 151 (0x97) 7?0 rhsb3ecnt[1?3][15:8] rhsb3ecnt[1?3][7:0] receive high-speed b3 error count. counts the number of b3 errors in the receive sts-3/ stm-1 (au-4) frame. only counter value 1 is valid in au-4 mode. this counter can either count actual bip errors or block errors (bitblockcnt, 0x34). this counter holds at its maximum value and transfers its internal count to a holding regis- ter when latch_cnt, 0x04 transitions from a logic 0 to 1. 0x0000 address dec (hex) bit name function reset default 152 (0x98) 153 (0x99) 2?0 7?0 rptr_inc1[10:8] rptr_inc1[7:0] receive pointer increment count. counts the number of increments in the incoming pointer val- ues. this counter holds at its maximum value and transfers its internal count to a holding register when latch_cnt, 0x04 transitions from a logic 0 to 1. 0x000 154 (0x9a) 155 (0x9b) 2?0 7?0 rptr_inc2[10:8] rptr_inc2[7:0] 156 (0x9c) 157 (0x9d) 2?0 7?0 rptr_inc3[10:8] rptr_inc3[7:0] 158 (0x9e) 159 (0x9f) 2?0 7?0 rptr_dec1[10:8] rptr_dec1[7:0] receive pointer decrement count. counts the number of decrements in the incoming pointer values. this counter holds at its maximum value and transfers its internal count to a holding regis- ter when latch_cnt, 0x04 transitions from a logic 0 to 1. 0x000 160 (0xa0) 161 (0xa1) 2?0 7?0 rptr_dec2[10:8] rptr_dec2[7:0] 162 (0xa2) 163 (0xa3) 2?0 7?0 rptr_dec3[10:8] rptr_dec3[7:0] address dec (hex) bit name function reset default 164 (0xa4) 165 (0xa5) 166 (0xa6) 1?0 7?0 7?0 rsfebecnt[17:16] rsfebecnt[15:8] rsfebecnt[7:0] receive section febe count. counts the num- ber of b2 errors received in the m1 byte of the receive sts-3/stm-1 (au-4) frame. this counter can either count actual sfebe errors or block errors (febebitblockcnt, 0x34). this counter holds at its maximum value and transfers its inter- nal count to a holding register when latch_cnt, 0x04 transitions from a logic 0 to 1. 0x00000
agere systems inc. 93 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) register map (continued) table 86. page 1 - registers 167?172: receive high-speed path febe count (ro) table 87. page 2 - register 131 (r/w) address dec (hex) bit name function reset default 167 (0xa7)? 172 (0xac) 7?0 rpfebecnt[1?3][15:8] rpfebecnt[1?3][7:0] receive path febe count. counts the number of b3 errors received in the g1[7:4] bits of the received sts-3/stm-1 (au-4) frame. this counter can either count actual pfebe errors or block errors (febebitblockcnt, 0x34). this counter holds at its maximum value and transfers its internal count to a holding register when latch_cnt, 0x04 transitions from a logic 0 to 1. 0x0000 address dec (hex) bit name function reset default 131 (0x83) 7 sdb1b2sel signal degrade b1/b2 error count select. control bit, when set to a logic 0, causes the sig- nal degrade bit error rate algorithm to use b1 errors; otherwise, b2 errors are used to calculate the error rate. 0
94 94 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) register map (continued) table 88. page 2 - registers 128?141 (r/w) set parameters are used when rhssd = 0, and the clear parameters are used when rhssd = 1. note: the thresholds written by the control system shall be one less than the desired number, except for the sdlset/clear[3:0] parameter. timing requirements: when sdset ( 0x04 ) is set to a 1, the device sets rhssd = 1, clears all remaining internal variables and counters of the rhssd algorithm, and initializes the algorithm to enable recovery declaration. when sdclear ( 0x04 ) is set to a 1, the device sets rhssd = 0, clears all remaining internal variables and counters of the rhssd algorithm and initializes the algorithm to enable failure declaration. if sdset or sdclear is cleared to 0, do nothing. if sdset and sdclear are simultaneously set to 1, do nothing. ber algorithm: while (sdl = 0) then disable algorithm and set rhssd , rhssdd = 0. address dec (hex) bit name function reset default 128 (0x80) 129 (0x81) 130 (0x82) 2?0 7?0 7?0 sdnsset[18:16] sdnsset[15:8] sdnsset[7:0] signal degrade ns set. number of frames in a monitoring block for rhssd, 0x1b. 0x00000 131 (0x83) 3?0 sdlset[3:0] signal degrade l set. error threshold for deter- mining if a monitoring block is bad. 0x0 132 (0x84) 7?0 sdmset[7:0] signal degrade m set. threshold of the number of bad monitoring blocks in an observation interval. if the number of bad blocks is above this threshold, then rhssd, 0x1b is set. 0x00 133 (0x85) 134 (0x86) 7?0 sdbset[15:8] sdbset[7:0] signal degrade b set. number of monitoring blocks. 0x0000 135 (0x87) 136 (0x88) 137 (0x89) 2?0 7?0 7?0 sdnsclear[18:16] sdnsclear[15:8] sdnsclear[7:0] signal degrade ns clear. number of frames in a monitoring block for rhssd, 0x1b. 0x00000 138 (0x8a) 3?0 sdlclear[3:0] signal degrade l clear. error threshold for deter- mining if a monitoring block is bad. 0x0 139 (0x8b) 7?0 sdmclear[7:0] signal degrade m clear. threshold of the number of good monitoring blocks in an observation inter- val. if the number of good blocks is above this threshold, then rhssd, 0x1b is cleared. 0x00 140 (0x8c) 141 (0x8d) 7?0 sdbclear[15:8] sdbclear[7:0] signal degrade b clear. number of monitoring blocks. 0x0000
agere systems inc. 95 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) register map (continued) if ( sdb1b2sel = 0) then use b1 bip errors in berr algorithm else use b2 bip errors in berr algorithm end if; if (newframe) then { incr (framecntr) biperr = biperr + newerr if (biperr > sdl ) then biperr = sdl if (framecntr = sdns ) then -- number of frames in monitoring block { reset (framecntr) if (biperr sdl ) then block = 1 /* indicates bad monitoring period. */ else block = 0 /* indicates good monitoring period. */ incr (btotcntr) reset (biperr) if ( rhssd = 0) then { if (block = 1) then { incr (bmoncntr) if (bmoncntr sdm ) then { rhssd = 1; rhssdd = 1 reset (bmoncntr); reset (btotcntr) } } else if (btotcntr = sdb ) then } reset (bmoncntr); reset (btotcntr) } }
96 96 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) register map (continued) if ( rhssd = 1) then { if (block = 0) then { incr (bmoncntr) if (bmoncntr sdm ) then { rhssd = 0; rhssdd = 1 reset (bmoncntr); reset (btotcntr) } } else if (btotcntr = sdb ) then { reset (bmoncntr); reset (btotcntr) } } } } where: newframe = checks for frame sync signal (internal) to reinitiate ber calculation. framecntr = count of number of frames since the start of the latest monitoring period. biperr = number of composite b1 or b2 errors so far in latest monitoring period. newerr = number of composite b1 or b2 errors calculated in latest frame. block = indication of good (0) or bad (1) latest monitoring period. btotcntr = count of current total number of monitoring periods (good or bad) in latest observation interval. bmoncntr = count of current number of: bad monitoring periods in latest observation interval if rhssd = 0, good monitoring periods in latest observation interval if rhssd = 1.
agere systems inc. 97 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) register map (continued) table 89. page 2 - register 145 (r/w) table 90. page 2 - registers 142?155 (r/w) the set parameters are used when rhssf = 0, and the clear parameters are used when rhssf = 1. note: the thresholds written by the control system shall be one less than the desired number, except for the sflset/clear[3:0] parameter. address dec (hex) bit name function reset default 145 (0x91) 7 sfb1b2sel signal fail b1/b2 error count select. control bit, when set to a logic 0, causes the signal fail bit error rate algorithm to use b1 errors; otherwise, b2 errors are used to calculate the error rate. 0 address dec (hex) bit name function reset default 142 (0x8e) 143 (0x8f) 144 (0x90) 2?0 7?0 7?0 sfnsset[18:16] sfnsset[15:8] sfnsset[7:0] signal fail ns set. number of frames in a monitor- ing block for rhssf, 0x1b. 0x00000 145 (0x91) 3?0 sflset[3:0] signal fail l set. error threshold for determining if a monitoring block is bad. 0x0 146 (0x92) 7?0 sfmset[7:0] signal fail m set. threshold of the number of bad monitoring blocks in an observation interval. if the number of bad blocks is above this threshold, then rhssf, 0x1b is set. 0x00 147 (0x93) 148 (0x94) 7?0 sfbset[15:8] sfbset[7:0] signal fail b set. number of monitoring blocks. 0x0000 150 (0x96) 151 (0x97) 152 (0x98) 2?0 7?0 7?0 sfnsclear[18:16] sfnsclear[15:8] sfnsclear[7:0] signal fail ns clear. number of frames in a moni- toring block for rhssf, 0x1b. 0x00000 152 (0x98) 3?0 sflclear[3:0] signal fail l clear. error threshold for determining if a monitoring block is bad. 0x0 153 (0x99) 7?0 sfmclear[7:0] signal fail m clear. threshold of the number of good monitoring blocks in an observation interval. if the number of good blocks is above this threshold, then rhssf, 0x1b is cleared. 0x00 154 (0x9a) 155 (0x9b) 7?0 sfbclear[15:8] sfbclear[7:0] signal fail b clear. number of monitoring blocks. 0x0000
98 98 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) register map (continued) timing requirements: when sfset is set to a 1, the device sets rhssf = 1, clears all remaining internal variables and counters of the rhssf algorithm and initializes the algorithm to enable recovery declaration. when sfclear is set to a 1, set rhssf = 0, clears all remaining internal variables and counters of the rhssf algorithm, and initializes the algorithm to enable failure declaration. if sfset or sfclear is cleared to a 0, do nothing. if sfset and sfclear are simultaneously set to a 1, do nothing. ber algorithm: while ( sfl = 0) then disable algorithm and set rhssf , rhssfd = 0.
agere systems inc. 99 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) register map (continued) if (sfb1b2sel = 0) then use b1 bip errors in ber algorithm else use b2 bip errors. if (newframe) then { incr (framecntr) biperr = biperr + newerr if (biperr > sfl ) then biperr = sfl if (framecntr = sfns ) then { reset (framecntr) if (biperr sfl ) then block = 1 /* indicates bad monitoring period. */ else block = 0 /* indicates good monitoring period. */ incr (btotcntr) reset (biperr) if ( rhssf = 0) then { if (block = 1) then { incr (bmoncntr) if (bmoncntr sfm ) then { rhssf = 1; rhssfd = 1 reset (bmoncntr); reset (btotcntr) } } else if (btotcntr = sfb3 ) then } reset (bmoncntr); reset (btotcntr) } }
100 100 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) register map (continued) if ( rhssf = 1) then { if (block = 0) then { incr (bmoncntr) if (bmoncntr msf ) then { rhssf = 0; rhssfd = 1 reset (bmoncntr); reset (btotcntr) } } else if (btotcntr = bsf ) then { reset (bmoncntr); reset (btotcntr) } } } } where: newframe = checks for frame sync signal (internal) to reinitiate ber calculation. framecntr = count of number of frames since the start of the latest monitoring period. biperr = number of composite b2 errors so far in latest monitoring period. newerr = number of composite b2 errors calculated in latest frame. block = indication of good(0) or bad(1) latest monitoring period. btotcntr = count of current total number of monitoring periods (good or bad) in latest observation interval. bmoncntr = count of current number of: bad monitoring periods in latest observation interval if rhssf = 0, good monitoring periods in latest observation interval if rhssf = 1.
agere systems inc. 101 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) i/o timing the i/o timing specifications for the microprocessor interface are given in table 92. the microprocessor interface pins use cmos i/o levels. all outputs, except the address/data bus ad[7:0], are rated for a capacitive load of 50 pf. the ad[7:0] outputs are rated for a 100 pf load. the minimum read and write cycle time is 200 ns for all device configurations. the read and write timing diagrams for all four microprocessor interface modes are shown in figures 7?14. table 91. microprocessor interface i/o timing specifications symbol configuration parameter setup (ns) (min) hold (ns) (min) delay (ns) (max) t1 modes 1 and 2 address valid to as asserted (read, write) 5?? t2 as asserted to address invalid (read, write) ?10? t3 as asserted to ds asserted 0?? t4 r/ w high (read) to ds asserted 25 ? ? t5 ds asserted (read, write) to dtack asserted ??20 t6 dtack asserted to data valid (read) ??24 t7 ds asserted (read) to data valid ??44 t8 ds negated (read, write) to as negated ??? t9 ds negated (read) to data invalid ??15 t10 ds negated (read) to dtack negated ??15 t11 as (read, write) asserted width ?55? t12 ds (read) asserted width ?25? t13 as asserted to r/ w low (write) 7?? t14 r/ w low (write) to ds asserted 20 ? ? t15 data valid to ds asserted (write) 7.5 ? ? t16 ds negated to dtack negated (write) ??20 t17 ds negated to data invalid (write) ??7.5 t18 ds (write) asserted width ?30? t19 modes 3 and 4 address valid to ale asserted low (read, write) 15 ? ? t20 ale asserted low (read, write) to address invalid ?10? t21 ale asserted low to rd asserted (read) 30 ? ? t22 rd asserted (read) to data valid ??90 t23 rd asserted (read) to rdy asserted ??75 t24 rd negated to data invalid (read) ??15 t25 rd negated to rdy negated (read) ??25 t26 ale asserted low to wr asserted (write) 35 ? ? t27 cs asserted to rdy asserted low ??16 t28 data valid to wr asserted (write) 25 ? ? t29 wr asserted (write) to rdy asserted ??73 t30 wr negated to rdy negated (write) ??22 t31 wr negated to data invalid ?25? t32 ale asserted (read, write) width ? 150 ? t33 rd asserted (read) width ? 100 ? t34 wr asserted (write) width ? 100 ?
102 102 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) i/o timing (continued) 5-3685(f).br.4 figure 7. mode 1?read cycle timing (mpmode = 0, mpmux = 0) 5-3686(f).br.5 figure 8. mode 1?write cycle timing (mpmode = 0, mpmux = 0) t6 t7 t5 ds as cs minimum read cycle valid address valid data a[7:0] r/w t2 t3 t10 t9 t8 t4 t12 ad[7:0] dtack t11 t1 t14 t5 t15 ds as cs minimum write cycle valid address valid data a[7:0] r/w t2 t1 t13 t16 t17 t8 t18 ad[7:0] dtack t11
agere systems inc. 103 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) i/o timing (continued) 5-3687(f)r.12 figure 9. mode 2?read cycle timing (mpmode = 0, mpmux = 1) 5-3688(f)r.12 figure 10. mode 2?write cycle timing (mpmode = 0, mpmux = 1) t6 t7 t5 ds as cs minimum read cycle valid data r/w t3 t10 t9 t8 t4 t12 ad[7:0] dtack t11 valid address valid address valid data t2 t1 valid address valid address valid data valid data cs as r/w ds dtack ad[7:0] minimum write cycle t11 t14 t8 t18 t16 t1 t13 t5 t2 t15 t17
104 104 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) i/o timing (continued) 5-3689(f).b * if ale is not used, the a[7:0] address bus must be valid t21 ns before rd is asserted low, and stay valid t25 ns after rd rises. figure 11. mode 3?read cycle timing (mpmode = 1, mpmux = 0) 5-3690(f).dr.4 * if ale is not used, the a[7:0] address bus must be valid t26 ns before wr is asserted low, and stay valid t31 ns after wr rises. figure 12. mode 3?write cycle timing (mpmode = 1, mpmux = 0) minimum read cycle t32 valid address ale* cs a[7:0] rd ad[7:0] rdy valid data t23 t25 t24 t22 t19 t27 t21 t20 t33 cs ale * a[7:0] wr ad[7:0] rdy minimum write cycle t19 t32 t20 valid address t28 t34 t26 t31 t29 t30 t27 valid data
agere systems inc. 105 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer microprocessor interface (continued) i/o timing (continued) 5-3691(f)r.12 figure 13. mode 4?read cycle timing (mpmode = 1, mpmux = 1) 5-3692(f)r.13 figure 14. mode 4?write cycle timing (mpmode = 1, mpmux = 1) cs ale rd ad[7:0] rdy minimum read cycle t32 t33 t22 t23 t25 t20 t27 t19 t21 t24 valid data valid data valid address valid address cs ale wr ad[7:0] rdy valid data valid address valid address valid data minimum write cycle t32 t26 t34 t29 t27 t30 t31 t28 t20 t19
106 106 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are abso- lute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. handling precautions although protection circuitry has been designed into this device, proper precautions should be taken to avoid expo- sure to electrostatic discharge (esd) during handling and mounting. agere employs a human-body model (hbm) and charged-device model (cdm) for esd-susceptibility testing and protection design evaluation. esd voltage thresholds are dependent on the circuit parameters used in the defined model. no industry-wide standard has been adopted for the cdm. however, a standard hbm (resistance = 1500 w, capacitance = 100 pf) is widely used and, therefore, can be used for comparison purposes. the hbm esd threshold presented here was obtained by using these circuit parameters: parameter symbol min max unit dc supply voltage range v dd ?0.5 4.6 v power dissipation p d ??mw storage temperature range t stg ?65 125 c ambient operating temperature range t a ?40 85 c maximum voltage (digital input pins) with respect to ref5vtol ??0.3v minimum voltage (digital input pins) with respect to v ss ??0.3? v device voltage TMUX03155 2500 v
agere systems inc. 107 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer operating conditions the following tables list the voltages required for proper operation of the TMUX03155 device, along with their toler- ances. table 92. recommended operating conditions parameter symbol min typ max unit power v dd 3.14 3.3 3.47 v ground v ss ?0.0 ? v input voltage, high v ih ?v dd ? 1.0 ref5vtol v input voltage, low v il ?v ss 1.0 v 5 v tolerant reference voltage 1 1. this input should be connected to 5.0 v when the device interfaces with 5 v and 3.3 v signals, or 3.3 v when the device only interfaces with 3.3 v signals. ref5vtol 4.75 5.0 5.25 v 3.3 v tolerant reference voltage * 3.14 3.3 3.47 v 1.0 v: lvds reference 2 2. use internal reference voltages if lvds_refsel = 0 or external voltage tolerance is > 5%. lvds_ref10 ? 1.0 ? v 1.4 v: lvds reference ? lvds_ref14 ? 1.4 ? v table 93. power measurements (v dd = 3.3 v, 23 c) device mode power unit sts-3/au-4 to/from sts-1/au-3 600 610 1 1. 85 c ambient temperature (not case temperature). mw sts-1/au-3 to sts-3/au-4 loopback (ths2rhslb = 1) 570 mw standby 550 mw
108 108 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer electrical characteristics * all outputs are 2 ma except tlsspeo, tlsj0j1vv1timeo, tlsv1timeo, thsssynco, thsdata[7:0]o, thsparo, rlsj0timeo, rlsdata[7:0]o, and rlsparo which are 4 ma buffers. the input specification for the remaining (nonbalanced) inputs are specified in figure 15 . see operational timing on page 110 5-6032(f)r.2 figure 15. single-ended input specification table 94. logic interface characteristics parameter symbol test conditions min max unit input leakage i l ??1.0a output current*: low high i ol i oh ? ? ? 2 2 ma ma output voltage: low high v ol v oh ?v ss v dd ? 0.5 0.5 ref5vtol v v input capacitance c i ? ?1.5pf v ih t f t r v il
agere systems inc. 109 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer electrical characteristics (continued) table 95. lvds interface characteristics 3.3 v 5% v dd , 0?125 c, slow?fast process . * buffer will not produce output transition when input is open-circuited. parameter symbol test conditions min typ max unit input buffer parameters input voltage range, v ia or v ib v i |v gpd | < 925 mv, dc?1 mhz 0.0 1.2 2.4 v input differential threshold v idth |v gpd | < 925 mv, 311 mhz ?100 ? 100 mv input differential hysteresis v hyst (+v idth ) ? (?v idth )???*mv receiver differential input impedance r in with build-in termination, center-tapped 80 100 120 ? output buffer parameters output voltage: low (v oa or v ob) high (v oa or v ob) v ol v oh r load = 100 ? 1% r load = 100 ? 1% ? 0.925 ? 1.475 ? v v output differential voltage |v od |r load = 100 ? 1% 0.25 ? 0.40 v output offset voltage v os r load = 100 ? 1% 1.125 ? 1.275 v output impedance, single ended r o v cm = 1.0 v and 1.4 v 40 50 60 ? r o mismatch between a and b ? r o v cm = 1.0 v and 1.4 v ? ? 10 % change in differential voltage between complementary states | ? v od |r load = 100 ? 1% ? ? 25 mv change in output offset voltage between complementary states ? v os r load = 100 ? 1% ? ? 25 mv output current i sa, i sb driver shorted to v ss ?? 24 ma output current i sab drivers shorted together ? ? 12 ma
110 110 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer timing characteristics operational timing the operational timing parameters can be grouped separately for clocks, inputs, and outputs. table 96 lists the input clock specifications for this device. the rise and fall times refer to the transition times from 10% to 90% of full swing. (for definitions of the signal names, see the pin descriptions in table 1, pages 10?15.) table 96. input clock specifications symbol parameter signal name min max unit f op operating frequency thssclkit/c 1 thsclki rhssclkit/c* rhsclk tclk 1. when the true and complement inputs are floating, the input buffer will not oscillate. ? ? ? ? ? 155.52 + 0.4% 38.88/19.44 + 1% 155.52 + 0.5% 38.88/19.44 + 1% 0.5?12 + 1% mhz mhz mhz mhz mhz t clkh clock pulse high time thssclkit/c* thsclki rhssclkit/c* rhsclk tclk 2.5 11.0/22.0 2.5 11.0/22.0 30 ? ? ? ? ? ns ns ns ns ns t r rise time thssclkit/c* thsclki rhssclkit/c* rhsclk tclk 1.5 3.5 1.5 3.5 15 ? ? ? ? ? ns ns ns ns ns t f fall time thssclkit/c* thsclki rhssclkit/c* rhsclk tclk 1.5 3.5 1.5 3.5 15 ? ? ? ? ? ns ns ns ns ns
agere systems inc. 111 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer timing characteristics (continued) operational timing (continued) the following table lists input setup and hold times and reference clocks. (see figure 17, interface data timing, on page 115.) table 97. input timing specifications input name reference clk setup time (t su ) hold time (t h ) unit min max min max transmit signals thssj0j1v1it/c* thssclkit/c 2.0 ? 0.0 ? ns thsj0j1v1i thsclki 2.0 0.0 ? ns transmit low-speed signals tlsdata[7:0]i tlsclko 5.0 ? 0.0 ? ns tlspari tlsclko 5.0 ? 0.0 ? ns transmit toac ttoacdatai ttoacclko 10.0 ? 10.0 ? ns receive signals rhssdatait/c 1 1. when the true and complement inputs are floating, the input buffer will not oscillate. rhssclkit/c 2.0 ? 0.0 ? ns rhsdata[7:0]i rhsclki 5.0 ? 0.0 ? ns rhspari rhsclki 5.0 ? 0.0 ? ns rhslosexti na async ? async ? ns jtag and scan tdi tclk 15 ? 15 ? ns tms tclk 15 ? 15 ? ns trst na async ? async ? ns scan_en na async ? async ? ns test_mode na async ? async ? ns miscellaneous mode [1:0] na async ? async ? ns reset na async ? async ? ns ict na async ? async ? ns
112 112 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer timing characteristics (continued) operational timing (continued) the following diagram defines the signal structure of the input signal thsj0j1v1i. figure 16. thsj0j1v1i signal structure definition * optional. ? msb = most significant bit, most significant byte, respectively; msn = most significant nibble. 5-6253 (f)r.2 frame superframe msb ? thsj0j1v1i clock cycles thsclktype = byte clock (19.44 mhz) 2430 clock cycles/frame (125 s) frame superframe thsj0j1v1i clock cycles thsclktype = nibble clock (38.88 mhz) 4860 clock cycles/frame (125 s) j0 j1 v1* j0 j1 j0 j1 j0 j1 v1* j0 j1 frame superframe msb ? thssj0j1v1it clock cycles 1 1 23 23 19392 19416 thsclktype = bit clock (155.52 mhz) 19440 clock cycles/frame (125 s) 123 19416 19416 11 23 23 123 123 500 s 125 s 125 s 125 s 125 s j0 j1 v1* j0 j1 j0 j1 j0 j1 v1* j0 j1 11 5 5 4848 4854 15 4854 4854 11 55 15 15 500 s 125 s 125 s 125 s 125 s msn ? j0 j1 v1* j0 j1 j0 j1 j0 j1 v1* j0 j1 11 2 2 2424 2427 12 2427 2427 11 22 12 12 500 s 125 s 125 s 125 s 125 s 1 1 1
agere systems inc. 113 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer timing characteristics (continued) operational timing (continued) the output clock specifications are shown in table 98. table 98. output clock specifications signal name reference clk 1 1. the specifications for the table are with all loopbacks disabled. frequency 2 2. the frequency percentages refer to the respective duty cycles. test conditions rise time fall time unit t r t f min max min max tlsclko thssclkit/c or thsclki 19.44 mhz 5% c l = 50 pf ? 3.5 ? 3.5 ns thssclko thssclkit/c 155.52 mhz 3% c l = 15 pf ? 1.5 ? 1.5 ns thsclko thssclkit/c or thsclki 38.88 mhz 5% or 19.44 mhz 5% c l = 15 pf ? 3.5 ? 3.5 ns ttoacclko thssclkit/c or thsclki 5.184 mhz 5% c l = 15 pf ? 3.5 ? 3.5 ns rlsclko rhssclkit/c or rhsclki or internal cdr clock 19.44 mhz 5% c l = 50 pf ? 3.5 ? 3.5 ns rtoacclko rhssclkit/c or rhsclki or internal cdr clock 5.184 mhz 5% c l = 15 pf ? 3.5 ? 3.5 ns
114 114 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer timing characteristics (continued) operational timing (continued) the following table lists the propagation delay specifications for the outputs. (see figure 17, interface data timing, on page 115. ) * propagation delay skew, t plh ?t phl, is 200 ps. table 99. output timing specifications output name reference clk test conditions propagation delay unit t pd min max transmit low-speed signals tlsspeo tlsclko c l = 50 pf 4.0 12.0 ns tlsj0j1v1timeo tlsclko c l = 50 pf 4.0 12.0 ns tlsv1timeo tlsclko c l = 50 pf 4.0 12.0 ns transmit high-speed signals thssclkit/c thssclkot/c c l = 15 pf 0.0 6.4 ns thsssyncot/c* thssclkot/c c l = 15 pf 0.6 2.9 ns thssdataot/c* thssclkot/c c l = 15 pf 0.6 2.9 ns thssynco thsclko c l = 15 pf 3.0 6.0 ns thsdata[7:0]o thsclko c l = 15 pf 3.0 6.0 ns thsparo thsclko c l = 15 pf 3.0 6.0 ns thsclki thsclko c l = 15 pf 3.0 7.8 ns transmit toac signal ttoacsynco ttoacclko c l = 15 pf 10.0 30.0 ns receive low-speed signals rlsj0timeo rlsclko c l = 50 pf 4.0 12.0 ns rlsdata[7:0]o rlsclko c l = 50 pf 4.0 12.0 ns rlsparo rlsclko c l = 50 pf 4.0 12.0 ns receive toac signals rtoacsynco rtoacclko c l = 15 pf 10.0 30.0 ns rtoacdatao rtoacclko c l = 15 pf 10.0 30.0 ns serial control interface (sci) intn async na async async ns jtag and scan tdo tclk c l = 25 pf 3.0 20.0 ns
agere systems inc. 115 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer timing characteristics (continued) operational timing (continued) a diagram of the digital system interface timing for setup and hold time input as well as propagation delay output specifications are shown in figure 17. the transmit and receive low-speed bus interfaces are shown in figure 18. 5-5342(f)r.1 figure 17. interface data timing clock data clock data t su t h t pd
116 116 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer timing characteristics (continued) operational timing (continued) 5-6255(f)r.5 * v1 time occurs once every 500 s. ? j0 time occurs once per frame (125 s). figure 18. bus interface signals tlsspeo tlsj0j1v1timeo tlsv1timeo* tlsdata[7:0]i rlsj0timeo ? rlsdata[7:0]o receive low-speed bus interface signals transmit low-speed bus interface signals j0-2 tlsclko rlsclko j0-1 j0-3 3 bytes 3 bytes 3 bytes 3 bytes 3 bytes a1 a2 j0 j1 v1 a1-2 a2-2 j0-2 j1-2 v1-3 v1-2 v1-1 j1-1 j1-3 j0-3 j0-1 a2-1 a2-3 a1-1 a1-3 j0 3 bytes
agere systems inc. 117 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer outline diagram 208-pin sqfp dimensions are in millimeters. 5-2196(f)1.3r.14 detail b 0.17/0.27 0.10 m 0.090/0.200 0.50/0.75 gage plane seating plane 1.30 ref 0.25 detail a 156 105 30.60 0.20 157 208 1 52 53 104 28.00 0.20 28.00 0.20 30.60 0.20 pin #1 identifier zone 4.10 max 0.08 3.40 0.20 seating plane 0.25 min 0.50 typ detail b detail a
118 118 agere systems inc. data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer ordering information ds01-194pdh replaces ds00-213tic to incorporate the following updates version 1 advisory (ay00-002sont) information incorporated into the datasheet. version id register value changed to 3 (see device version and device id number on page 29). for au-4 mode, the b3 error count register (rei-p) mechanism was changed so that the transmit clock has enough time to sample the value for application on the outgoing g1[7:4] bits. the transitioning in the loss of pointer (lop) state was fixed for the ndf condition. device code package temperature comcode TMUX03155 208-pin sqfp ?40 c to +85 c 108126368-db
agere systems inc. 119 data sheet april 2001 TMUX03155 sts-3/stm-1 (au-4) multiplexer/demultiplexer notes
agere systems inc. reserves the right to make changes to the product(s) or information contained herein without notice. no liab ility is assumed as a result of their use or application. copyright ? 2001 agere systems inc. all rights reserved printed in u.s.a. april 2001 ds01-194pdh (replaces ds99-213tic) for additional information, contact your agere systems account manager or the following: internet: http://www.agere.com e-mail: docmaster@micro.lucent.com n. america: agere systems inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18109-3286 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia pacific: agere systems singapore pte. ltd., 77 science park drive, #03-18 cintech iii, singapore 118256 tel. (65) 778 8833 , fax (65) 777 7495 china: agere systems (shanghai) co., ltd., 33/f jin mao tower, 88 century boulevard pudong, shanghai 200121 prc tel. (86) 21 50471212 , fax (86) 21 50472266 japan: agere systems japan ltd., 7-18, higashi-gotanda 2-chome, shinagawa-ku, tokyo 141, japan tel. (81) 3 5421 1600 , fax (81) 3 5421 1700 europe: data requests: dataline: tel. (44) 7000 582 368 , fax (44) 1189 328 148 technical inquiries:germany: (49) 89 95086 0 (munich), united kingdom: (44) 1344 865 900 (ascot), france: (33) 1 40 83 68 00 (paris), sweden: (46) 8 594 607 00 (stockholm), finland: (358) 9 3507670 (helsinki), italy: (39) 02 6608131 (milan), spain: (34) 1 807 1441 (madrid)

▲Up To Search▲

Price & Availability of TMUX03155

	To Download TMUX03155 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .